Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3615259	1			T80	2169		T81	98		T82	836
values[2]	724513	1			T80	592		T81	52		T82	63
values[3]	101288	1			T82	3		T86	2		T252	2
values[4]	54702	1			T472	2		T559	407		T473	1
values[5]	36264	1			T559	256		T878	9		T568	517
values[6]	27333	1			T559	175		T878	10		T568	308
values[7]	21802	1			T559	123		T878	8		T568	141
values[8]	18641	1			T559	87		T878	8		T568	74
values[9]	16459	1			T559	63		T878	5		T568	70
values[10]	14880	1			T559	72		T878	10		T568	88
values[11]	13656	1			T559	52		T878	10		T568	71
values[12]	12695	1			T559	35		T878	15		T568	55
values[13]	12301	1			T559	26		T878	16		T568	53
values[14]	11981	1			T559	57		T878	7		T568	57
values[15]	11736	1			T559	39		T878	2		T568	43
values[16]	10867	1			T559	17		T878	1		T568	44
values[17]	10450	1			T559	6		T878	2		T568	50
values[18]	10012	1			T559	4		T878	1		T568	44
values[19]	9601	1			T559	10		T878	3		T568	26
values[20]	9552	1			T559	18		T878	1		T568	33
values[21]	9228	1			T559	18		T878	1		T568	43
values[22]	8963	1			T559	5		T878	2		T568	30
values[23]	8624	1			T559	3		T878	1		T568	25
values[24]	8535	1			T559	6		T878	3		T568	23
values[25]	8199	1			T559	5		T878	1		T568	24
values[26]	7674	1			T559	5		T878	3		T568	20
values[27]	7264	1			T559	6		T878	2		T568	21
values[28]	7074	1			T559	3		T878	1		T568	42
values[29]	6768	1			T559	6		T878	2		T568	60
values[30]	6471	1			T559	11		T878	5		T568	58
values[31]	5921	1			T559	11		T878	2		T568	64
values[32]	5590	1			T559	4		T568	27		T449	20
values[33]	4945	1			T559	5		T568	29		T449	16
values[34]	4528	1			T559	3		T568	13		T449	21
values[35]	4311	1			T559	5		T568	23		T449	18
values[36]	4164	1			T559	8		T568	24		T449	16
values[37]	4035	1			T559	12		T568	14		T449	17
values[38]	3797	1			T559	10		T568	7		T449	10
values[39]	3658	1			T559	9		T568	9		T449	23
values[40]	3449	1			T559	8		T568	12		T449	18
values[41]	3359	1			T559	4		T568	9		T449	12
values[42]	3316	1			T559	10		T568	13		T449	9
values[43]	3179	1			T559	11		T568	13		T449	25
values[44]	3203	1			T559	14		T568	14		T449	24
values[45]	3069	1			T559	8		T568	7		T449	19
values[46]	3115	1			T559	4		T568	7		T449	21
values[47]	2947	1			T559	5		T568	13		T449	15
values[48]	2969	1			T559	8		T568	9		T449	9
values[49]	2908	1			T559	5		T568	6		T449	10
values[50]	2804	1			T559	5		T568	8		T449	4
values[51]	2722	1			T559	6		T568	10		T449	12
values[52]	2663	1			T559	9		T568	10		T449	9
values[53]	2631	1			T559	4		T568	11		T449	4
values[54]	2610	1			T559	5		T568	11		T449	10
values[55]	2511	1			T559	7		T568	6		T449	14
values[56]	2392	1			T559	5		T568	13		T449	8
values[57]	2463	1			T559	3		T568	11		T449	8
values[58]	2454	1			T559	5		T568	11		T449	7
values[59]	2426	1			T559	7		T568	14		T449	8
values[60]	2356	1			T559	5		T568	6		T449	5
values[61]	2614	1			T559	11		T568	11		T449	2
values[62]	4040	1			T559	25		T568	37		T449	1
values[63]	15755	1			T559	67		T568	123		T449	5
values[64]	221606	1			T559	124		T568	361		T449	125

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4654996	1			T80	2167		T81	149		T82	805
values[2]	760362	1			T80	572		T81	36		T82	55
values[3]	75740	1			T80	17		T82	6		T86	4
values[4]	13971	1			T80	2		T253	2		T472	50
values[5]	5313	1			T80	2		T472	16		T559	21
values[6]	3076	1			T80	1		T472	5		T559	8
values[7]	2451	1			T472	3		T559	4		T568	2
values[8]	2052	1			T472	1		T568	1		T449	3
values[9]	1716	1			T472	1		T568	1		T449	1
values[10]	1627	1			T472	1		T568	2		T449	4
values[11]	1436	1			T568	1		T449	5		T421	18
values[12]	1255	1			T568	1		T449	3		T421	13
values[13]	1147	1			T568	1		T449	1		T421	19
values[14]	1139	1			T568	1		T449	1		T421	38
values[15]	1036	1			T568	1		T449	2		T421	20
values[16]	878	1			T568	1		T449	2		T421	11
values[17]	831	1			T568	1		T449	1		T421	4
values[18]	850	1			T568	2		T449	1		T421	5
values[19]	765	1			T568	3		T449	1		T421	3
values[20]	770	1			T568	2		T449	2		T421	6
values[21]	718	1			T568	1		T449	3		T421	4
values[22]	659	1			T568	2		T449	2		T421	2
values[23]	660	1			T568	1		T449	2		T421	4
values[24]	636	1			T568	1		T449	3		T421	5
values[25]	657	1			T568	2		T449	3		T421	1
values[26]	676	1			T568	2		T449	1		T421	1
values[27]	621	1			T568	1		T449	1		T421	3
values[28]	646	1			T568	1		T449	1		T421	2
values[29]	656	1			T568	1		T449	1		T421	2
values[30]	608	1			T568	2		T449	3		T421	1
values[31]	633	1			T568	1		T449	2		T421	8
values[32]	573	1			T568	1		T449	1		T421	3
values[33]	502	1			T568	1		T449	1		T421	3
values[34]	500	1			T568	1		T449	2		T421	3
values[35]	466	1			T568	1		T449	2		T421	1
values[36]	473	1			T568	1		T449	4		T421	5
values[37]	466	1			T568	1		T449	3		T421	5
values[38]	447	1			T568	1		T449	2		T421	5
values[39]	480	1			T568	2		T449	2		T421	10
values[40]	466	1			T568	2		T449	6		T421	4
values[41]	407	1			T568	2		T449	1		T421	2
values[42]	425	1			T568	1		T449	2		T421	1
values[43]	404	1			T568	1		T449	1		T421	1
values[44]	401	1			T568	3		T449	1		T421	1
values[45]	377	1			T568	1		T449	2		T421	1
values[46]	391	1			T568	1		T449	1		T421	3
values[47]	385	1			T568	1		T449	3		T421	2
values[48]	369	1			T568	1		T449	2		T421	1
values[49]	385	1			T568	1		T449	1		T421	2
values[50]	383	1			T568	1		T449	1		T421	7
values[51]	393	1			T568	1		T449	2		T421	5
values[52]	374	1			T568	2		T449	7		T421	1
values[53]	359	1			T568	1		T449	2		T421	5
values[54]	338	1			T568	1		T449	1		T421	4
values[55]	353	1			T568	2		T449	1		T421	8
values[56]	365	1			T568	1		T449	2		T421	2
values[57]	372	1			T568	6		T449	2		T421	1
values[58]	342	1			T568	2		T449	1		T421	1
values[59]	332	1			T568	3		T449	1		T421	2
values[60]	329	1			T568	4		T449	3		T421	2
values[61]	368	1			T568	7		T449	1		T421	4
values[62]	577	1			T568	15		T449	2		T421	2
values[63]	2466	1			T568	48		T449	10		T421	8
values[64]	25279	1			T568	78		T449	111		T421	25

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	650009	1			T80	20		T81	1		T82	41
values[2]	2515835	1			T80	2171		T81	75		T82	337
values[3]	1092889	1			T80	573		T81	33		T82	488
values[4]	146582	1			T80	3		T82	6		T86	3
values[5]	73718	1			T559	420		T578	9		T579	5
values[6]	48046	1			T559	299		T878	10		T568	442
values[7]	34724	1			T559	185		T878	6		T568	227
values[8]	27986	1			T559	143		T878	14		T568	174
values[9]	23437	1			T559	116		T878	11		T568	119
values[10]	20057	1			T559	123		T878	7		T568	122
values[11]	17882	1			T559	113		T878	7		T568	114
values[12]	16559	1			T559	135		T878	7		T568	103
values[13]	15393	1			T559	80		T878	12		T568	90
values[14]	14986	1			T559	51		T878	7		T568	108
values[15]	14097	1			T559	30		T878	4		T568	112
values[16]	13453	1			T559	19		T878	12		T568	74
values[17]	12899	1			T559	18		T878	8		T568	68
values[18]	12052	1			T559	6		T878	5		T568	77
values[19]	11916	1			T559	11		T878	3		T568	121
values[20]	11313	1			T559	12		T878	1		T568	106
values[21]	11175	1			T559	11		T878	3		T568	131
values[22]	10631	1			T559	7		T878	8		T568	106
values[23]	10250	1			T559	6		T878	4		T568	78
values[24]	9607	1			T559	14		T878	3		T568	89
values[25]	9380	1			T559	8		T878	6		T568	90
values[26]	8918	1			T559	14		T878	5		T568	64
values[27]	8317	1			T559	6		T878	4		T568	60
values[28]	7990	1			T559	3		T878	2		T568	59
values[29]	7276	1			T559	6		T568	51		T449	19
values[30]	6905	1			T559	4		T568	48		T449	5
values[31]	6302	1			T559	3		T568	44		T449	7
values[32]	5775	1			T559	7		T568	44		T449	8
values[33]	5512	1			T559	7		T568	27		T449	10
values[34]	5286	1			T559	12		T568	26		T449	1
values[35]	4817	1			T559	8		T568	23		T449	1
values[36]	4518	1			T559	16		T568	26		T449	4
values[37]	4291	1			T559	8		T568	31		T449	2
values[38]	4166	1			T559	8		T568	42		T449	1
values[39]	3922	1			T559	10		T568	39		T449	2
values[40]	3708	1			T559	7		T568	34		T449	1
values[41]	3590	1			T559	11		T568	25		T449	1
values[42]	3515	1			T559	10		T568	22		T449	2
values[43]	3358	1			T559	9		T568	18		T449	1
values[44]	3351	1			T559	16		T568	14		T449	1
values[45]	3399	1			T559	14		T568	10		T449	1
values[46]	3345	1			T559	17		T568	12		T449	2
values[47]	3183	1			T559	11		T568	10		T449	2
values[48]	3175	1			T559	9		T568	15		T449	2
values[49]	3156	1			T559	8		T568	11		T449	1
values[50]	3115	1			T559	4		T568	12		T449	1
values[51]	3146	1			T559	6		T568	10		T449	1
values[52]	3028	1			T559	13		T568	13		T449	3
values[53]	3019	1			T559	14		T568	11		T449	1
values[54]	2914	1			T559	23		T568	18		T449	2
values[55]	2658	1			T559	10		T568	32		T449	3
values[56]	2781	1			T559	14		T568	33		T449	1
values[57]	2711	1			T559	8		T568	18		T449	3
values[58]	2624	1			T559	5		T568	15		T449	1
values[59]	2622	1			T559	8		T568	18		T449	1
values[60]	2601	1			T559	7		T568	19		T449	1
values[61]	2832	1			T559	9		T568	17		T449	2
values[62]	3811	1			T559	14		T568	16		T449	2
values[63]	17526	1			T559	34		T568	73		T449	1
values[64]	211063	1			T559	41		T568	296		T449	149