Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2132306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31976102

1

T4

5387

T5

7023

T6

17939

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23038006	1			T4	1973		T5	3192		T6	7798
values[0x0]	9249139	1			T4	3414		T5	3831		T6	10141
values[0x1]	1821263	1			T4	265		T5	375		T6	1270

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	483013	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

33625395

1

T4

5652

T5

7398

T6

19209

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16096748	1			T4	2826		T5	3699		T6	9605
valid_sources[0x01]	16095475	1			T4	2826		T5	3699		T6	9604
valid_sources[0x02]	31818	1			T75	2		T85	1		T12	3
valid_sources[0x03]	30567	1			T75	1		T12	1		T908	20
valid_sources[0x04]	31279	1			T198	1		T199	3		T908	196
valid_sources[0x05]	30924	1			T75	3		T85	2		T199	1
valid_sources[0x06]	30759	1			T85	1		T586	1		T147	65
valid_sources[0x07]	30972	1			T908	198		T147	90		T587	19
valid_sources[0x08]	30418	1			T75	2		T198	2		T908	52
valid_sources[0x09]	30802	1			T85	1		T147	140		T587	11
valid_sources[0x0a]	30523	1			T199	1		T12	2		T586	1
valid_sources[0x0b]	30475	1			T85	1		T147	105		T587	12
valid_sources[0x0c]	31247	1			T75	1		T908	16		T147	115
valid_sources[0x0d]	31145	1			T85	2		T199	3		T147	89
valid_sources[0x0e]	30823	1			T198	5		T199	2		T908	40
valid_sources[0x0f]	31391	1			T75	1		T12	3		T908	106
valid_sources[0x10]	30907	1			T85	2		T199	6		T908	218
valid_sources[0x11]	29937	1			T84	6		T85	1		T199	2
valid_sources[0x12]	31258	1			T75	2		T198	1		T908	157
valid_sources[0x13]	31247	1			T198	3		T12	3		T908	158
valid_sources[0x14]	31000	1			T147	68		T587	14		T580	39
valid_sources[0x15]	30218	1			T75	1		T12	3		T908	159
valid_sources[0x16]	31300	1			T199	2		T147	113		T587	8
valid_sources[0x17]	30028	1			T75	1		T85	1		T198	4
valid_sources[0x18]	31161	1			T75	1		T908	171		T586	3
valid_sources[0x19]	31172	1			T75	1		T84	7		T85	2
valid_sources[0x1a]	30591	1			T12	1		T908	86		T586	3
valid_sources[0x1b]	30615	1			T75	1		T84	6		T908	210
valid_sources[0x1c]	30763	1			T908	452		T586	12		T147	93
valid_sources[0x1d]	30914	1			T75	1		T586	14		T147	58
valid_sources[0x1e]	30753	1			T84	3		T85	1		T198	4
valid_sources[0x1f]	30533	1			T84	9		T85	3		T908	44
valid_sources[0x20]	30686	1			T75	1		T85	1		T199	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22529289

1

T4

1973

T5

3192

T6

7798

values[0x0]

all_enables

biggest_size

9209893

1

T4

3414

T5

3831

T6

10141

values[0x1]

all_enables

biggest_size

236920

1

T75

24

T84

19

T85

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2820768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

447267

1

T80

387

T81

29

T82

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1106757	1			T80	921		T81	48		T82	19
values[0x0]	1055342	1			T80	908		T81	57		T82	7
values[0x1]	1105936	1			T80	932		T81	45		T82	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2185238	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1082797

1

T80

920

T81

57

T82

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51901	1			T80	28		T86	1		T252	3
valid_sources[0x01]	51420	1			T80	44		T81	15		T82	1
valid_sources[0x02]	50852	1			T80	41		T86	2		T252	1
valid_sources[0x03]	51525	1			T80	49		T86	1		T252	2
valid_sources[0x04]	51641	1			T80	52		T82	1		T86	1
valid_sources[0x05]	52226	1			T80	56		T86	1		T252	2
valid_sources[0x06]	51313	1			T80	29		T86	2		T472	90
valid_sources[0x07]	50209	1			T80	41		T472	12		T559	53
valid_sources[0x08]	50941	1			T80	53		T86	2		T472	16
valid_sources[0x09]	50463	1			T80	49		T86	1		T252	7
valid_sources[0x0a]	51354	1			T80	59		T86	2		T252	4
valid_sources[0x0b]	49816	1			T80	26		T81	3		T86	1
valid_sources[0x0c]	49940	1			T80	41		T86	1		T252	2
valid_sources[0x0d]	50597	1			T80	69		T81	9		T82	1
valid_sources[0x0e]	50814	1			T80	49		T81	2		T82	1
valid_sources[0x0f]	52643	1			T80	36		T81	4		T86	3
valid_sources[0x10]	50862	1			T80	44		T82	2		T86	1
valid_sources[0x11]	50518	1			T80	53		T81	5		T86	1
valid_sources[0x12]	50646	1			T80	45		T81	6		T82	3
valid_sources[0x13]	51254	1			T80	35		T86	2		T252	2
valid_sources[0x14]	51503	1			T80	36		T86	2		T252	1
valid_sources[0x15]	51070	1			T80	42		T86	1		T252	1
valid_sources[0x16]	50992	1			T80	51		T82	2		T86	3
valid_sources[0x17]	51251	1			T80	41		T82	1		T86	3
valid_sources[0x18]	52865	1			T80	34		T81	3		T86	4
valid_sources[0x19]	51089	1			T80	33		T86	3		T252	2
valid_sources[0x1a]	52105	1			T80	35		T81	3		T86	4
valid_sources[0x1b]	50352	1			T80	41		T86	3		T472	23
valid_sources[0x1c]	51317	1			T80	41		T81	1		T86	2
valid_sources[0x1d]	50550	1			T80	40		T81	7		T252	7
valid_sources[0x1e]	51334	1			T80	56		T81	14		T82	2
valid_sources[0x1f]	52367	1			T80	44		T86	2		T252	2
valid_sources[0x20]	51121	1			T80	56		T82	3		T86	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46977

1

T80

45

T81

4

T82

2

values[0x0]

all_enables

biggest_size

353580

1

T80

306

T81

22

T82

3

values[0x1]

all_enables

biggest_size

46710

1

T80

36

T81

3

T82

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3005771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

489557

1

T80

388

T81

21

T82

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1196253	1			T80	927		T81	70		T82	22
values[0x0]	1103179	1			T80	929		T81	45		T82	1
values[0x1]	1195896	1			T80	905		T81	70		T82	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2306578	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1188750

1

T80

901

T81

69

T82

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55260	1			T80	64		T81	4		T86	4
valid_sources[0x01]	54832	1			T80	42		T81	2		T82	1
valid_sources[0x02]	53793	1			T80	35		T81	6		T252	3
valid_sources[0x03]	55136	1			T80	37		T81	3		T86	1
valid_sources[0x04]	55594	1			T80	35		T81	8		T472	47
valid_sources[0x05]	54617	1			T80	30		T81	1		T86	2
valid_sources[0x06]	54480	1			T80	39		T81	3		T82	1
valid_sources[0x07]	54559	1			T80	52		T81	3		T86	2
valid_sources[0x08]	54193	1			T80	46		T81	3		T86	1
valid_sources[0x09]	55477	1			T80	45		T81	3		T86	3
valid_sources[0x0a]	54205	1			T80	41		T81	2		T86	1
valid_sources[0x0b]	55054	1			T80	44		T81	2		T82	1
valid_sources[0x0c]	54350	1			T80	42		T81	2		T86	3
valid_sources[0x0d]	54353	1			T80	55		T82	1		T253	1
valid_sources[0x0e]	54338	1			T80	32		T81	1		T86	1
valid_sources[0x0f]	54520	1			T80	42		T81	6		T86	2
valid_sources[0x10]	54525	1			T80	48		T81	6		T82	1
valid_sources[0x11]	54566	1			T80	38		T81	4		T86	3
valid_sources[0x12]	54856	1			T80	47		T81	2		T86	2
valid_sources[0x13]	55031	1			T80	40		T81	3		T82	1
valid_sources[0x14]	54057	1			T80	45		T81	2		T86	1
valid_sources[0x15]	53881	1			T80	65		T82	2		T252	3
valid_sources[0x16]	53595	1			T80	59		T81	1		T82	3
valid_sources[0x17]	54926	1			T80	48		T81	4		T82	2
valid_sources[0x18]	55256	1			T80	47		T81	2		T252	2
valid_sources[0x19]	55110	1			T80	41		T81	6		T82	1
valid_sources[0x1a]	55885	1			T80	44		T81	3		T252	4
valid_sources[0x1b]	54233	1			T80	45		T81	2		T86	2
valid_sources[0x1c]	54437	1			T80	45		T81	1		T86	3
valid_sources[0x1d]	53972	1			T80	45		T81	2		T86	1
valid_sources[0x1e]	54449	1			T80	34		T81	3		T86	2
valid_sources[0x1f]	54244	1			T80	39		T81	2		T86	1
valid_sources[0x20]	55203	1			T80	38		T81	2		T86	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51221

1

T80

35

T81

1

T86

3

values[0x0]

all_enables

biggest_size

386846

1

T80

311

T81

16

T82

1

values[0x1]

all_enables

biggest_size

51490

1

T80

42

T81

4

T86

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2844914	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

450135

1

T80

371

T81

9

T82

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1115210	1			T80	924		T81	41		T82	14
values[0x0]	1064652	1			T80	931		T81	27		T82	2
values[0x1]	1115187	1			T80	912		T81	41		T82	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2203731	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1091318

1

T80

872

T81

37

T82

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51471	1			T80	56		T82	1		T252	5
valid_sources[0x01]	50971	1			T80	36		T86	3		T252	1
valid_sources[0x02]	51527	1			T80	50		T81	2		T86	4
valid_sources[0x03]	51761	1			T80	39		T81	2		T86	2
valid_sources[0x04]	52227	1			T80	34		T81	3		T82	1
valid_sources[0x05]	51931	1			T80	26		T472	13		T559	65
valid_sources[0x06]	51321	1			T80	43		T472	25		T559	85
valid_sources[0x07]	51272	1			T80	33		T81	5		T86	2
valid_sources[0x08]	51982	1			T80	32		T81	1		T82	1
valid_sources[0x09]	51465	1			T80	43		T81	6		T82	2
valid_sources[0x0a]	51529	1			T80	45		T81	5		T86	3
valid_sources[0x0b]	50641	1			T80	40		T81	5		T86	6
valid_sources[0x0c]	51084	1			T80	33		T86	1		T472	59
valid_sources[0x0d]	52086	1			T80	58		T81	3		T86	1
valid_sources[0x0e]	51240	1			T80	54		T82	1		T86	3
valid_sources[0x0f]	52524	1			T80	39		T81	3		T82	1
valid_sources[0x10]	51127	1			T80	39		T81	4		T82	1
valid_sources[0x11]	50805	1			T80	43		T86	1		T252	2
valid_sources[0x12]	52207	1			T80	38		T81	1		T86	1
valid_sources[0x13]	50682	1			T80	42		T82	2		T86	1
valid_sources[0x14]	50645	1			T80	42		T81	2		T86	10
valid_sources[0x15]	50946	1			T80	49		T81	6		T82	2
valid_sources[0x16]	50864	1			T80	43		T86	1		T253	1
valid_sources[0x17]	51995	1			T80	39		T81	5		T252	3
valid_sources[0x18]	52358	1			T80	37		T81	2		T82	1
valid_sources[0x19]	52592	1			T80	42		T81	1		T86	1
valid_sources[0x1a]	51743	1			T80	44		T81	1		T86	1
valid_sources[0x1b]	50871	1			T80	44		T81	4		T472	53
valid_sources[0x1c]	51069	1			T80	40		T86	2		T252	1
valid_sources[0x1d]	51035	1			T80	44		T81	3		T86	2
valid_sources[0x1e]	51704	1			T80	43		T81	1		T472	60
valid_sources[0x1f]	52220	1			T80	50		T81	4		T86	1
valid_sources[0x20]	52396	1			T80	36		T81	2		T86	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47086

1

T80

43

T82

1

T86

3

values[0x0]

all_enables

biggest_size

355740

1

T80

296

T81

8

T82

1

values[0x1]

all_enables

biggest_size

47309

1

T80

32

T81

1

T86

6