Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	79.17			79.17
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17			79.17

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17			79.17

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.91	99.17	84.51	98.84		80.03	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.30	99.83	66.67	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T63,T75,T223	Yes	T63,T75,T223	INPUT
alert_req_i	Yes	Yes	T20,T248,T109	Yes	T20,T68,T248	INPUT
alert_ack_o	Yes	Yes	T20,T68,T248	Yes	T20,T68,T248	OUTPUT
alert_state_o	Yes	Yes	T20,T248,T109	Yes	T20,T68,T248	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T87,T63,T75	Yes	T87,T63,T75	INPUT
alert_rx_i.ping_n	Yes	Yes	T87,T88,T89	Yes	T88,T89,T90	INPUT
alert_rx_i.ping_p	Yes	Yes	T88,T89,T90	Yes	T87,T88,T89	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T87,T63,T75	Yes	T87,T63,T75	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	9	75.00
Total Bits	24	19	79.17
Total Bits 0->1	12	10	83.33
Total Bits 1->0	12	9	75.00

Ports	12	9	75.00
Port Bits	24	19	79.17
Port Bits 0->1	12	10	83.33
Port Bits 1->0	12	9	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T65,T66,T12	Yes	T65,T66,T12	INPUT
alert_req_i	No	No		Yes	T388	INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T88,T65,T89	Yes	T88,T65,T89	INPUT
alert_rx_i.ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i.ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T88,T65,T89	Yes	T88,T65,T89	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T65,T66,T67	Yes	T65,T66,T67	INPUT
alert_req_i	Yes	Yes	T92,T93,T96	Yes	T92,T93,T94	INPUT
alert_ack_o	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	OUTPUT
alert_state_o	Yes	Yes	T92,T93,T96	Yes	T92,T93,T94	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T87,T88,T65	Yes	T87,T88,T65	INPUT
alert_rx_i.ping_n	Yes	Yes	T87,T88,T89	Yes	T88,T89,T90	INPUT
alert_rx_i.ping_p	Yes	Yes	T88,T89,T90	Yes	T87,T88,T89	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T87,T88,T65	Yes	T87,T88,T65	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T75,T65,T66	Yes	T75,T65,T66	INPUT
alert_req_i	Yes	Yes	T313,T314,T315	Yes	T312,T313,T314	INPUT
alert_ack_o	Yes	Yes	T312,T313,T314	Yes	T312,T313,T314	OUTPUT
alert_state_o	Yes	Yes	T313,T314,T315	Yes	T312,T313,T314	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T75,T312,T313	Yes	T75,T312,T313	INPUT
alert_rx_i.ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i.ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T75,T312,T313	Yes	T75,T312,T313	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T65,T66,T67	Yes	T65,T66,T67	INPUT
alert_req_i	Yes	Yes	T724,T725	Yes	T724,T725	INPUT
alert_ack_o	Yes	Yes	T724,T725	Yes	T724,T725	OUTPUT
alert_state_o	Yes	Yes	T724,T725	Yes	T724,T725	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T88,T65,T89	Yes	T88,T65,T89	INPUT
alert_rx_i.ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i.ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T88,T65,T89	Yes	T88,T65,T89	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T63,T223,T65	Yes	T63,T223,T65	INPUT
alert_req_i	Yes	Yes	T12	Yes	T12	INPUT
alert_ack_o	Yes	Yes	T12	Yes	T12	OUTPUT
alert_state_o	Yes	Yes	T12	Yes	T12	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T63,T223,T88	Yes	T63,T223,T88	INPUT
alert_rx_i.ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i.ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T63,T223,T88	Yes	T63,T223,T88	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T65,T66,T67	Yes	T65,T66,T67	INPUT
alert_req_i	Yes	Yes	T20,T248,T109	Yes	T20,T68,T248	INPUT
alert_ack_o	Yes	Yes	T20,T68,T248	Yes	T20,T68,T248	OUTPUT
alert_state_o	Yes	Yes	T20,T248,T109	Yes	T20,T68,T248	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T20,T68,T248	Yes	T20,T68,T248	INPUT
alert_rx_i.ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i.ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T20,T68,T248	Yes	T20,T68,T248	OUTPUT