Unified Coverage Report :: Module :: ibex_top

Module : ibex_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.16			94.16

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_core	96.51			96.51

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.51			96.51

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.51			96.51

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : ibex_top

	Total	Covered	Percent
Totals	40	33	82.50
Total Bits	822	774	94.16
Total Bits 0->1	411	388	94.40
Total Bits 1->0	411	386	93.92

Ports	40	33	82.50
Port Bits	822	774	94.16
Port Bits 0->1	411	388	94.40
Port Bits 1->0	411	386	93.92

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
instr_gnt_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_rvalid_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[16:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
instr_addr_o[18:17]	No	No		No		OUTPUT
instr_addr_o[19]	No	No		Yes	T60,T386,T387	OUTPUT
instr_addr_o[27:20]	No	No		No		OUTPUT
instr_addr_o[29:28]	Yes	Yes	*T109,*T179,*T58	Yes	T109,T179,T58	OUTPUT
instr_addr_o[31:30]	No	No		No		OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_err_i	Yes	Yes	T20,T191,T222	Yes	T20,T191,T222	INPUT
data_req_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_gnt_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_rvalid_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_we_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_be_o[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_wdata_o[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_wdata_intg_o[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_rdata_i[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_err_i	Yes	Yes	T20,T47,T70	Yes	T20,T47,T70	INPUT
irq_software_i	Yes	Yes	T254,T113,T255	Yes	T254,T113,T255	INPUT
irq_timer_i	Yes	Yes	T256,T154,T257	Yes	T256,T154,T257	INPUT
irq_external_i	Yes	Yes	T6,T19,T20	Yes	T6,T19,T20	INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	Yes	Yes	T20,T47,T171	Yes	T20,T47,T171	INPUT
scramble_key_valid_i	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	INPUT
scramble_key_i[127:0]	Yes	Yes	T6,T59,T64	Yes	T6,T59,T121	INPUT
scramble_nonce_i[63:0]	Yes	Yes	T6,T59,T19	Yes	T4,T5,T6	INPUT
scramble_req_o	Yes	Yes	T179,T180,T181	Yes	T179,T180,T181	OUTPUT
debug_req_i	Yes	Yes	T76,T259,T260	Yes	T76,T259,T260	INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	Yes	Yes	T20,T248,T249	Yes	T20,T248,T249	OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T6,T20,T68	Yes	T4,T5,T6	INPUT
alert_minor_o	No	No		Yes	T388	OUTPUT
alert_major_internal_o	Yes	Yes	T389,T390,T388	Yes	T389,T390,T388	OUTPUT
alert_major_bus_o	Yes	Yes	T109,T246,T247	Yes	T109,T246,T247	OUTPUT
core_sleep_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

	Total	Covered	Percent
Totals	36	33	91.67
Total Bits	802	774	96.51
Total Bits 0->1	401	388	96.76
Total Bits 1->0	401	386	96.26

Ports	36	33	91.67
Port Bits	802	774	96.51
Port Bits 0->1	401	388	96.76
Port Bits 1->0	401	386	96.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
instr_gnt_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_rvalid_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[16:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
instr_addr_o[18:17]	No	No		No		OUTPUT
instr_addr_o[19]	No	No		Yes	T60,T386,T387	OUTPUT
instr_addr_o[27:20]	No	No		No		OUTPUT
instr_addr_o[29:28]	Yes	Yes	*T109,*T179,*T58	Yes	T109,T179,T58	OUTPUT
instr_addr_o[31:30]	No	No		No		OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_err_i	Yes	Yes	T20,T191,T222	Yes	T20,T191,T222	INPUT
data_req_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_gnt_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_rvalid_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_we_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_be_o[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_wdata_o[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_wdata_intg_o[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_rdata_i[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_err_i	Yes	Yes	T20,T47,T70	Yes	T20,T47,T70	INPUT
irq_software_i	Yes	Yes	T254,T113,T255	Yes	T254,T113,T255	INPUT
irq_timer_i	Yes	Yes	T256,T154,T257	Yes	T256,T154,T257	INPUT
irq_external_i	Yes	Yes	T6,T19,T20	Yes	T6,T19,T20	INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	Yes	Yes	T20,T47,T171	Yes	T20,T47,T171	INPUT
scramble_key_valid_i	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	INPUT
scramble_key_i[127:0]	Yes	Yes	T6,T59,T64	Yes	T6,T59,T121	INPUT
scramble_nonce_i[63:0]	Yes	Yes	T6,T59,T19	Yes	T4,T5,T6	INPUT
scramble_req_o	Yes	Yes	T179,T180,T181	Yes	T179,T180,T181	OUTPUT
debug_req_i	Yes	Yes	T76,T259,T260	Yes	T76,T259,T260	INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	Yes	Yes	T20,T248,T249	Yes	T20,T248,T249	OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T6,T20,T68	Yes	T4,T5,T6	INPUT
alert_minor_o	No	No		Yes	T388	OUTPUT
alert_major_internal_o	Yes	Yes	T389,T390,T388	Yes	T389,T390,T388	OUTPUT
alert_major_bus_o	Yes	Yes	T109,T246,T247	Yes	T109,T246,T247	OUTPUT
core_sleep_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range