Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456445288	52025339	0	0
DepthKnown_A	456445288	456340154	0	0
RvalidKnown_A	456445288	456340154	0	0
WreadyKnown_A	456445288	456340154	0	0
gen_passthru_fifo.paramCheckPass	991	991	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	52025339	0	0
T4	200245	25907	0	0
T5	83408	9040	0	0
T6	309563	33960	0	0
T19	214166	23177	0	0
T20	250185	25257	0	0
T59	124781	135547	0	0
T62	341160	3461	0	0
T64	194678	25156	0	0
T68	136451	21263	0	0
T91	182508	224250	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456445288	39650355	0	0
DepthKnown_A	456445288	456340154	0	0
RvalidKnown_A	456445288	456340154	0	0
WreadyKnown_A	456445288	456340154	0	0
gen_passthru_fifo.paramCheckPass	991	991	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	39650355	0	0
T4	200245	23274	0	0
T5	83408	6752	0	0
T6	309563	26675	0	0
T19	214166	19334	0	0
T20	250185	18533	0	0
T59	124781	118003	0	0
T62	341160	1868	0	0
T64	194678	22535	0	0
T68	136451	14687	0	0
T91	182508	206812	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456445288	38288816	0	0
DepthKnown_A	456445288	456340154	0	0
RvalidKnown_A	456445288	456340154	0	0
WreadyKnown_A	456445288	456340154	0	0
gen_passthru_fifo.paramCheckPass	991	991	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	38288816	0	0
T4	200245	5856	0	0
T5	83408	7758	0	0
T6	309563	19650	0	0
T19	214166	18700	0	0
T20	250185	12753	0	0
T59	124781	194357	0	0
T62	341160	459	0	0
T64	194678	5327	0	0
T68	136451	7422	0	0
T91	182508	525763	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456445288	32221660	0	0
DepthKnown_A	456445288	456340154	0	0
RvalidKnown_A	456445288	456340154	0	0
WreadyKnown_A	456445288	456340154	0	0
gen_passthru_fifo.paramCheckPass	991	991	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	32221660	0	0
T4	200245	5652	0	0
T5	83408	7398	0	0
T6	309563	19209	0	0
T19	214166	17852	0	0
T20	250185	12423	0	0
T59	124781	110953	0	0
T62	341160	351	0	0
T64	194678	5124	0	0
T68	136451	7148	0	0
T91	182508	525096	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	456340154	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522715865	78038	0	0
DepthKnown_A	522715865	522598694	0	0
RvalidKnown_A	522715865	522598694	0	0
WreadyKnown_A	522715865	522598694	0	0
gen_passthru_fifo.paramCheckPass	2881	2881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	78038	0	0
T4	200245	78	0	0
T5	83408	14	0	0
T6	309563	64	0	0
T19	214166	22	0	0
T20	250185	102	0	0
T59	124781	34	0	0
T62	341160	8	0	0
T64	194678	78	0	0
T68	136451	26	0	0
T91	182508	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2881	2881	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522715865	80145	0	0
DepthKnown_A	522715865	522598694	0	0
RvalidKnown_A	522715865	522598694	0	0
WreadyKnown_A	522715865	522598694	0	0
gen_passthru_fifo.paramCheckPass	2881	2881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	80145	0	0
T4	200245	78	0	0
T5	83408	14	0	0
T6	309563	64	0	0
T19	214166	22	0	0
T20	250185	102	0	0
T59	124781	34	0	0
T62	341160	8	0	0
T64	194678	78	0	0
T68	136451	26	0	0
T91	182508	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2881	2881	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522715865	50281	0	0
DepthKnown_A	522715865	522598694	0	0
RvalidKnown_A	522715865	522598694	0	0
WreadyKnown_A	522715865	522598694	0	0
gen_passthru_fifo.paramCheckPass	2881	2881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	50281	0	0
T4	200245	77	0	0
T5	83408	13	0	0
T6	309563	59	0	0
T19	214166	19	0	0
T20	250185	94	0	0
T59	124781	5	0	0
T62	341160	8	0	0
T64	194678	77	0	0
T68	136451	23	0	0
T91	182508	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2881	2881	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522715865	50281	0	0
DepthKnown_A	522715865	522598694	0	0
RvalidKnown_A	522715865	522598694	0	0
WreadyKnown_A	522715865	522598694	0	0
gen_passthru_fifo.paramCheckPass	2881	2881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	50281	0	0
T4	200245	77	0	0
T5	83408	13	0	0
T6	309563	59	0	0
T19	214166	19	0	0
T20	250185	94	0	0
T59	124781	5	0	0
T62	341160	8	0	0
T64	194678	77	0	0
T68	136451	23	0	0
T91	182508	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2881	2881	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522715865	27757	0	0
DepthKnown_A	522715865	522598694	0	0
RvalidKnown_A	522715865	522598694	0	0
WreadyKnown_A	522715865	522598694	0	0
gen_passthru_fifo.paramCheckPass	2881	2881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	27757	0	0
T4	200245	1	0	0
T5	83408	1	0	0
T6	309563	5	0	0
T19	214166	3	0	0
T20	250185	8	0	0
T59	124781	29	0	0
T62	341160	0	0	0
T64	194678	1	0	0
T68	136451	3	0	0
T91	182508	55	0	0
T127	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2881	2881	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522715865	29864	0	0
DepthKnown_A	522715865	522598694	0	0
RvalidKnown_A	522715865	522598694	0	0
WreadyKnown_A	522715865	522598694	0	0
gen_passthru_fifo.paramCheckPass	2881	2881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	29864	0	0
T4	200245	1	0	0
T5	83408	1	0	0
T6	309563	5	0	0
T19	214166	3	0	0
T20	250185	8	0	0
T59	124781	29	0	0
T62	341160	0	0	0
T64	194678	1	0	0
T68	136451	3	0	0
T91	182508	55	0	0
T127	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522715865	522598694	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2881	2881	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0