Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.28			98.28

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon	100.00			100.00
tb.dut.top_earlgrey.u_sram_ctrl_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.36	89.96		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.36	89.96		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	64	60	93.75
Total Bits	1160	1140	98.28
Total Bits 0->1	580	570	98.28
Total Bits 1->0	580	570	98.28

Ports	64	60	93.75
Port Bits	1160	1140	98.28
Port Bits 0->1	580	570	98.28
Port Bits 1->0	580	570	98.28

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[16:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
ram_tl_i.a_address[20:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[27:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T6,T20,T47	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
ram_tl_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T59,*T60,*T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T75,*T76,*T83	Yes	T75,T76,T83	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T75,T84,T85	Yes	T75,T84,T85	INPUT
regs_tl_i.a_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_o.a_ready	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
regs_tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T75,T179,T176	Yes	T75,T179,T176	OUTPUT
regs_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T56,T57,T75	Yes	T59,T60,T61	OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T56,T57,T75	Yes	T59,T60,T61	OUTPUT
regs_tl_o.d_sink	Yes	Yes	T80,T82,T86	Yes	T80,T81,T82	OUTPUT
regs_tl_o.d_source[5:0]	Yes	Yes	*T75,*T12,*T80	Yes	T75,T12,T80	OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T82,T86	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T75,*T179,*T176	Yes	T75,T179,T456	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T88,T65,T89	Yes	T88,T65,T89	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T88,T65,T89	Yes	T88,T65,T89	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T20,T47,T70	Yes	T20,T47,T70	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T6,T20,T47	INPUT
sram_otp_key_o.req	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T6,T59,T19	Yes	T4,T5,T6	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T6,T59,T64	Yes	T6,T59,T121	INPUT
sram_otp_key_i.ack	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.ram_cfg.cfg_en	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

	Total	Covered	Percent
Totals	58	58	100.00
Total Bits	1098	1098	100.00
Total Bits 0->1	549	549	100.00
Total Bits 1->0	549	549	100.00

Ports	58	58	100.00
Port Bits	1098	1098	100.00
Port Bits 0->1	549	549	100.00
Port Bits 1->0	549	549	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T59,T20	Yes	T6,T59,T20	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[11:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
ram_tl_i.a_address[20:12]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T75,*T76,*T83	Yes	T75,T76,T83	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T75,T84,T85	Yes	T75,T84,T85	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T6,T20,T47	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T59,T20	Yes	T6,T59,T20	OUTPUT
ram_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T6,T59,T20	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T6,T59,T20	Yes	T6,T59,T20	OUTPUT
ram_tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
ram_tl_o.d_source[5:0]	Yes	Yes	*T84,*T85,*T199	Yes	T84,T85,T199	OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
regs_tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T75,*T76,*T83	Yes	T75,T76,T83	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T75,T84,T85	Yes	T75,T84,T85	INPUT
regs_tl_i.a_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_o.a_ready	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
regs_tl_o.d_error	Yes	Yes	T80,T82,T86	Yes	T80,T81,T82	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T75,T176,T177	Yes	T75,T176,T177	OUTPUT
regs_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T56,T57,T75	Yes	T59,T60,T61	OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T56,T57,T75	Yes	T59,T60,T61	OUTPUT
regs_tl_o.d_sink	Yes	Yes	T80,T82,T86	Yes	T80,T82,T86	OUTPUT
regs_tl_o.d_source[5:0]	Yes	Yes	*T75,*T12,*T80	Yes	T75,T12,T80	OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T82,T86	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T75,*T176,*T177	Yes	T75,T456,T176	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T88,T65,T89	Yes	T88,T65,T89	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T88,T65,T89	Yes	T88,T65,T89	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T20,T47,T70	Yes	T20,T47,T70	INPUT
lc_hw_debug_en_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
otp_en_sram_ifetch_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
sram_otp_key_o.req	Yes	Yes	T176,T177,T178	Yes	T176,T177,T178	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T6,T59,T19	Yes	T4,T5,T6	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T6,T59,T64	Yes	T6,T59,T121	INPUT
sram_otp_key_i.ack	Yes	Yes	T176,T177,T178	Yes	T176,T177,T178	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

	Total	Covered	Percent
Totals	60	60	100.00
Total Bits	1132	1132	100.00
Total Bits 0->1	566	566	100.00
Total Bits 1->0	566	566	100.00

Ports	60	60	100.00
Port Bits	1132	1132	100.00
Port Bits 0->1	566	566	100.00
Port Bits 1->0	566	566	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[16:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
ram_tl_i.a_address[27:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[31:29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T6,T20,T47	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
ram_tl_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T6,T59,T20	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T59,*T60,*T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T59,*T60,*T61	Yes	T59,T60,T61	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T75,*T12,*T80	Yes	T75,T12,T80	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T80,T82,T86	Yes	T80,T82,T86	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
regs_tl_i.a_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
regs_tl_o.a_ready	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
regs_tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T82,T86	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T75,T179,T303	Yes	T75,T179,T303	OUTPUT
regs_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T56,T57,T75	Yes	T59,T60,T61	OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T56,T57,T75	Yes	T59,T60,T61	OUTPUT
regs_tl_o.d_sink	Yes	Yes	T80,T82,T86	Yes	T80,T81,T82	OUTPUT
regs_tl_o.d_source[5:0]	Yes	Yes	*T75,*T12,*T80	Yes	T75,T12,T80	OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T80,T82,T86	Yes	T80,T82,T86	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T75,*T179,*T177	Yes	T75,T179,T456	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T88,T65,T89	Yes	T88,T65,T89	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T89,T90	Yes	T88,T89,T90	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T88,T65,T89	Yes	T88,T65,T89	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T20,T47,T70	Yes	T20,T47,T70	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T6,T20,T47	INPUT
sram_otp_key_o.req	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T6,T20,T47	Yes	T4,T5,T6	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T6,T59,T19	Yes	T4,T5,T6	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T6,T59,T64	Yes	T6,T59,T121	INPUT
sram_otp_key_i.ack	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range