Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T181,T12
0	1	Covered	T180,T181,T293
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T293
1	Covered	T180,T181,T12

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T293
1	Covered	T180,T181,T12

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T181,T293
1	1	Covered	T180,T181,T293

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T181,T12
1	0	Covered	T180,T181,T293
1	1	Covered	T180,T181,T293

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T180,T181,T293

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T12
0	Covered	T180,T181,T293

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T12
0	Covered	T180,T181,T293

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	912890576	893096374	0	0
CheckNGreaterZero_A	1982	1982	0	0
GntImpliesReady_A	912890576	8443	0	0
GntImpliesValid_A	912890576	8443	0	0
GrantKnown_A	912890576	893096374	0	0
IdxKnown_A	912890576	893096374	0	0
IndexIsCorrect_A	912890576	8443	0	0
NoReadyValidNoGrant_A	912890576	0	0	0
Priority_A	912890576	8443	0	0
ReadyAndValidImplyGrant_A	912890576	8443	0	0
ReqAndReadyImplyGrant_A	912890576	8443	0	0
ReqImpliesValid_A	912890576	8443	0	0
ValidKnown_A	912890576	893096374	0	0
gen_data_port_assertion.DataFlow_A	912890576	8443	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	893096374	0	0
T4	400490	400388	0	0
T5	166816	166692	0	0
T6	619126	618792	0	0
T19	428332	428230	0	0
T20	500370	500150	0	0
T59	249562	249550	0	0
T62	682320	682204	0	0
T64	389356	389240	0	0
T68	272902	272792	0	0
T91	365016	365002	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1982	1982	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T59	2	2	0	0
T62	2	2	0	0
T64	2	2	0	0
T68	2	2	0	0
T91	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	8443	0	0
T89	298214	0	0	0
T180	155306	2806	0	0
T181	0	2817	0	0
T293	0	2820	0	0
T295	522508	0	0	0
T296	176774	0	0	0
T297	172922	0	0	0
T298	1212848	0	0	0
T299	178636	0	0	0
T300	1748300	0	0	0
T301	247206	0	0	0
T302	428928	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	8443	0	0
T89	298214	0	0	0
T180	155306	2806	0	0
T181	0	2817	0	0
T293	0	2820	0	0
T295	522508	0	0	0
T296	176774	0	0	0
T297	172922	0	0	0
T298	1212848	0	0	0
T299	178636	0	0	0
T300	1748300	0	0	0
T301	247206	0	0	0
T302	428928	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	893096374	0	0
T4	400490	400388	0	0
T5	166816	166692	0	0
T6	619126	618792	0	0
T19	428332	428230	0	0
T20	500370	500150	0	0
T59	249562	249550	0	0
T62	682320	682204	0	0
T64	389356	389240	0	0
T68	272902	272792	0	0
T91	365016	365002	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	893096374	0	0
T4	400490	400388	0	0
T5	166816	166692	0	0
T6	619126	618792	0	0
T19	428332	428230	0	0
T20	500370	500150	0	0
T59	249562	249550	0	0
T62	682320	682204	0	0
T64	389356	389240	0	0
T68	272902	272792	0	0
T91	365016	365002	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	8443	0	0
T89	298214	0	0	0
T180	155306	2806	0	0
T181	0	2817	0	0
T293	0	2820	0	0
T295	522508	0	0	0
T296	176774	0	0	0
T297	172922	0	0	0
T298	1212848	0	0	0
T299	178636	0	0	0
T300	1748300	0	0	0
T301	247206	0	0	0
T302	428928	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	8443	0	0
T89	298214	0	0	0
T180	155306	2806	0	0
T181	0	2817	0	0
T293	0	2820	0	0
T295	522508	0	0	0
T296	176774	0	0	0
T297	172922	0	0	0
T298	1212848	0	0	0
T299	178636	0	0	0
T300	1748300	0	0	0
T301	247206	0	0	0
T302	428928	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	8443	0	0
T89	298214	0	0	0
T180	155306	2806	0	0
T181	0	2817	0	0
T293	0	2820	0	0
T295	522508	0	0	0
T296	176774	0	0	0
T297	172922	0	0	0
T298	1212848	0	0	0
T299	178636	0	0	0
T300	1748300	0	0	0
T301	247206	0	0	0
T302	428928	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	8443	0	0
T89	298214	0	0	0
T180	155306	2806	0	0
T181	0	2817	0	0
T293	0	2820	0	0
T295	522508	0	0	0
T296	176774	0	0	0
T297	172922	0	0	0
T298	1212848	0	0	0
T299	178636	0	0	0
T300	1748300	0	0	0
T301	247206	0	0	0
T302	428928	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	8443	0	0
T89	298214	0	0	0
T180	155306	2806	0	0
T181	0	2817	0	0
T293	0	2820	0	0
T295	522508	0	0	0
T296	176774	0	0	0
T297	172922	0	0	0
T298	1212848	0	0	0
T299	178636	0	0	0
T300	1748300	0	0	0
T301	247206	0	0	0
T302	428928	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	893096374	0	0
T4	400490	400388	0	0
T5	166816	166692	0	0
T6	619126	618792	0	0
T19	428332	428230	0	0
T20	500370	500150	0	0
T59	249562	249550	0	0
T62	682320	682204	0	0
T64	389356	389240	0	0
T68	272902	272792	0	0
T91	365016	365002	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	912890576	8443	0	0
T89	298214	0	0	0
T180	155306	2806	0	0
T181	0	2817	0	0
T293	0	2820	0	0
T295	522508	0	0	0
T296	176774	0	0	0
T297	172922	0	0	0
T298	1212848	0	0	0
T299	178636	0	0	0
T300	1748300	0	0	0
T301	247206	0	0	0
T302	428928	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T181,T12
0	1	Covered	T180,T181,T293
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T293
1	Covered	T180,T181,T12

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T293
1	Covered	T180,T181,T12

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T181,T293
1	1	Covered	T180,T181,T293

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T181,T12
1	0	Covered	T180,T181,T293
1	1	Covered	T180,T181,T293

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T180,T181,T293

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T12
0	Covered	T180,T181,T293

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T12
0	Covered	T180,T181,T293

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456445288	446548187	0	0
CheckNGreaterZero_A	991	991	0	0
GntImpliesReady_A	456445288	5258	0	0
GntImpliesValid_A	456445288	5258	0	0
GrantKnown_A	456445288	446548187	0	0
IdxKnown_A	456445288	446548187	0	0
IndexIsCorrect_A	456445288	5258	0	0
NoReadyValidNoGrant_A	456445288	0	0	0
Priority_A	456445288	5258	0	0
ReadyAndValidImplyGrant_A	456445288	5258	0	0
ReqAndReadyImplyGrant_A	456445288	5258	0	0
ReqImpliesValid_A	456445288	5258	0	0
ValidKnown_A	456445288	446548187	0	0
gen_data_port_assertion.DataFlow_A	456445288	5258	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	446548187	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	5258	0	0
T89	149107	0	0	0
T180	77653	1744	0	0
T181	0	1755	0	0
T293	0	1759	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	5258	0	0
T89	149107	0	0	0
T180	77653	1744	0	0
T181	0	1755	0	0
T293	0	1759	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	446548187	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	446548187	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	5258	0	0
T89	149107	0	0	0
T180	77653	1744	0	0
T181	0	1755	0	0
T293	0	1759	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	5258	0	0
T89	149107	0	0	0
T180	77653	1744	0	0
T181	0	1755	0	0
T293	0	1759	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	5258	0	0
T89	149107	0	0	0
T180	77653	1744	0	0
T181	0	1755	0	0
T293	0	1759	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	5258	0	0
T89	149107	0	0	0
T180	77653	1744	0	0
T181	0	1755	0	0
T293	0	1759	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	5258	0	0
T89	149107	0	0	0
T180	77653	1744	0	0
T181	0	1755	0	0
T293	0	1759	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	446548187	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	5258	0	0
T89	149107	0	0	0
T180	77653	1744	0	0
T181	0	1755	0	0
T293	0	1759	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T181,T12
0	1	Covered	T180,T181,T293
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T293
1	Covered	T180,T181,T12

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T181,T293
1	Covered	T180,T181,T12

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T181,T293
1	1	Covered	T180,T181,T293

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T181,T12
1	0	Covered	T180,T181,T293
1	1	Covered	T180,T181,T293

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T180,T181,T293

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T12
0	Covered	T180,T181,T293

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T181,T12
0	Covered	T180,T181,T293

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456445288	446548187	0	0
CheckNGreaterZero_A	991	991	0	0
GntImpliesReady_A	456445288	3185	0	0
GntImpliesValid_A	456445288	3185	0	0
GrantKnown_A	456445288	446548187	0	0
IdxKnown_A	456445288	446548187	0	0
IndexIsCorrect_A	456445288	3185	0	0
NoReadyValidNoGrant_A	456445288	0	0	0
Priority_A	456445288	3185	0	0
ReadyAndValidImplyGrant_A	456445288	3185	0	0
ReqAndReadyImplyGrant_A	456445288	3185	0	0
ReqImpliesValid_A	456445288	3185	0	0
ValidKnown_A	456445288	446548187	0	0
gen_data_port_assertion.DataFlow_A	456445288	3185	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	446548187	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T64	1	1	0	0
T68	1	1	0	0
T91	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	3185	0	0
T89	149107	0	0	0
T180	77653	1062	0	0
T181	0	1062	0	0
T293	0	1061	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	3185	0	0
T89	149107	0	0	0
T180	77653	1062	0	0
T181	0	1062	0	0
T293	0	1061	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	446548187	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	446548187	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	3185	0	0
T89	149107	0	0	0
T180	77653	1062	0	0
T181	0	1062	0	0
T293	0	1061	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	3185	0	0
T89	149107	0	0	0
T180	77653	1062	0	0
T181	0	1062	0	0
T293	0	1061	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	3185	0	0
T89	149107	0	0	0
T180	77653	1062	0	0
T181	0	1062	0	0
T293	0	1061	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	3185	0	0
T89	149107	0	0	0
T180	77653	1062	0	0
T181	0	1062	0	0
T293	0	1061	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	3185	0	0
T89	149107	0	0	0
T180	77653	1062	0	0
T181	0	1062	0	0
T293	0	1061	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	446548187	0	0
T4	200245	200194	0	0
T5	83408	83346	0	0
T6	309563	309396	0	0
T19	214166	214115	0	0
T20	250185	250075	0	0
T59	124781	124775	0	0
T62	341160	341102	0	0
T64	194678	194620	0	0
T68	136451	136396	0	0
T91	182508	182501	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456445288	3185	0	0
T89	149107	0	0	0
T180	77653	1062	0	0
T181	0	1062	0	0
T293	0	1061	0	0
T295	261254	0	0	0
T296	88387	0	0	0
T297	86461	0	0	0
T298	606424	0	0	0
T299	89318	0	0	0
T300	874150	0	0	0
T301	123603	0	0	0
T302	214464	0	0	0