Unified Coverage Report :: Module :: chip_earlgrey_asic

Module : chip_earlgrey_asic

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.90	80.00	100.00	95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.83	80.00	100.00	98.48

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.83	80.00	100.00	98.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.37	95.60	94.23	95.49		95.03	96.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
top_earlgrey	95.33	95.54	93.78	95.47		94.84	97.02
u_ast	94.79			94.79
u_padring	97.80	99.21	99.81	96.57		99.60	93.81
u_prim_usb_diff_rx	96.30	100.00	88.89			100.00

Line Coverage for Module : chip_earlgrey_asic

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	789	1	0	0.00
CONT_ASSIGN	800	1	0	0.00
CONT_ASSIGN	825	1	0	0.00
CONT_ASSIGN	832	1	0	0.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	842	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	854	1	0	0.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1024	1	1	100.00
CONT_ASSIGN	1025	1	1	100.00
CONT_ASSIGN	1032	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
CONT_ASSIGN	1050	1	1	100.00
CONT_ASSIGN	1051	1	1	100.00
CONT_ASSIGN	1052	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00
CONT_ASSIGN	1057	1	1	100.00
CONT_ASSIGN	1058	1	1	100.00
CONT_ASSIGN	1059	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
214	1	1
215	1	1
789	0	1
800	0	1
825	0	1
832	0	1
839	1	1
842	1	1
848	1	1
850	1	1
854	0	1
857	1	1
1022	1	1
1023	1	1
1024	1	1
1025	1	1
1032	1	1
1049	1	1
1050	1	1
1051	1	1
1052	1	1
1056	1	1
1057	1	1
1058	1	1
1059	1	1

---

Cond Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T68,T126

---

Toggle Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Totals	70	64	91.43
Total Bits	140	134	95.71
Total Bits 0->1	70	70	100.00
Total Bits 1->0	70	64	91.43

Ports	70	64	91.43
Port Bits	140	134	95.71
Port Bits 0->1	70	70	100.00
Port Bits 1->0	70	64	91.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
POR_N	Yes	Yes	T21,T22,T23	Yes	T4,T5,T6	INOUT
USB_P	Yes	Yes	T32,T33,T37	Yes	T32,T33,T37	INOUT
USB_N	Yes	Yes	T32,T33,T37	Yes	T32,T33,T37	INOUT
CC1	No	No		Yes	T24,T25,T26	INOUT
CC2	No	No		Yes	T24,T25,T26	INOUT
FLASH_TEST_VOLT	No	No		Yes	T24,T25,T26	INOUT
FLASH_TEST_MODE0	No	No		Yes	T24,T25,T26	INOUT
FLASH_TEST_MODE1	No	No		Yes	T24,T25,T26	INOUT
OTP_EXT_VOLT	No	No		Yes	T24,T25,T26	INOUT
SPI_HOST_D0	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INOUT
SPI_HOST_D1	Yes	Yes	T27,T28,T29	Yes	T27,T24,T28	INOUT
SPI_HOST_D2	Yes	Yes	T27,T188,T189	Yes	T27,T188,T189	INOUT
SPI_HOST_D3	Yes	Yes	T27,T188,T189	Yes	T27,T188,T189	INOUT
SPI_HOST_CLK	Yes	Yes	T27,T28,T29	Yes	T27,T24,T28	INOUT
SPI_HOST_CS_L	Yes	Yes	T27,T75,T28	Yes	T27,T75,T24	INOUT
SPI_DEV_D0	Yes	Yes	T27,T28,T83	Yes	T27,T28,T83	INOUT
SPI_DEV_D1	Yes	Yes	T27,T28,T83	Yes	T27,T28,T83	INOUT
SPI_DEV_D2	Yes	Yes	T27,T188,T189	Yes	T27,T188,T25	INOUT
SPI_DEV_D3	Yes	Yes	T27,T188,T189	Yes	T27,T188,T189	INOUT
SPI_DEV_CLK	Yes	Yes	T27,T28,T83	Yes	T27,T24,T28	INOUT
SPI_DEV_CS_L	Yes	Yes	T27,T24,T28	Yes	T27,T24,T28	INOUT
IOR8	Yes	Yes	T107,T202,T34	Yes	T107,T3,T202	INOUT
IOR9	Yes	Yes	T202,T34,T35	Yes	T50,T107,T3	INOUT
IOA0	Yes	Yes	T30,T31,T2	Yes	T30,T31,T24	INOUT
IOA1	Yes	Yes	T30,T31,T2	Yes	T30,T31,T2	INOUT
IOA2	Yes	Yes	T31,T2,T208	Yes	T31,T2,T208	INOUT
IOA3	Yes	Yes	T31,T2,T13	Yes	T31,T24,T2	INOUT
IOA4	Yes	Yes	T31,T2,T207	Yes	T31,T2,T207	INOUT
IOA5	Yes	Yes	T31,T2,T207	Yes	T31,T2,T207	INOUT
IOA6	Yes	Yes	T31,T2,T13	Yes	T31,T2,T13	INOUT
IOA7	Yes	Yes	T19,T31,T2	Yes	T19,T31,T2	INOUT
IOA8	Yes	Yes	T19,T31,T2	Yes	T19,T31,T2	INOUT
IOB0	Yes	Yes	T48,T49,T46	Yes	T24,T48,T26	INOUT
IOB1	Yes	Yes	T48,T49,T46	Yes	T48,T25,T49	INOUT
IOB2	Yes	Yes	T46,T43,T44	Yes	T25,T46,T43	INOUT
IOB3	Yes	Yes	T107,T48,T202	Yes	T107,T48,T202	INOUT
IOB4	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	INOUT
IOB5	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	INOUT
IOB6	Yes	Yes	T107,T31,T202	Yes	T107,T31,T202	INOUT
IOB7	Yes	Yes	T1,T31,T10	Yes	T50,T1,T31	INOUT
IOB8	Yes	Yes	T107,T31,T202	Yes	T107,T31,T202	INOUT
IOB9	Yes	Yes	T216,T31,T342	Yes	T216,T31,T24	INOUT
IOB10	Yes	Yes	T216,T31,T218	Yes	T216,T31,T218	INOUT
IOB11	Yes	Yes	T31,T218,T208	Yes	T31,T218,T208	INOUT
IOB12	Yes	Yes	T31,T218,T208	Yes	T31,T218,T208	INOUT
IOC0	Yes	Yes	T59,T60,T61	Yes	T83,T152,T269	INOUT
IOC1	Yes	Yes	T83,T152,T219	Yes	T83,T152,T219	INOUT
IOC2	Yes	Yes	T83,T152,T219	Yes	T24,T83,T152	INOUT
IOC3	Yes	Yes	T124,T220,T354	Yes	T124,T220,T354	INOUT
IOC4	Yes	Yes	T124,T56,T57	Yes	T124,T56,T57	INOUT
IOC5	Yes	Yes	T62,T73,T74	Yes	T62,T73,T74	INOUT
IOC6	Yes	Yes	T4,T64,T124	Yes	T4,T64,T124	INOUT
IOC7	Yes	Yes	T107,T202,T34	Yes	T32,T107,T33	INOUT
IOC8	Yes	Yes	T62,T73,T74	Yes	T62,T73,T74	INOUT
IOC9	Yes	Yes	T50,T107,T31	Yes	T50,T107,T31	INOUT
IOC10	Yes	Yes	T31,T218,T208	Yes	T31,T218,T208	INOUT
IOC11	Yes	Yes	T31,T218,T208	Yes	T31,T218,T208	INOUT
IOC12	Yes	Yes	T31,T218,T208	Yes	T31,T24,T218	INOUT
IOR0	Yes	Yes	T62,T21,T63	Yes	T62,T21,T63	INOUT
IOR1	Yes	Yes	T62,T21,T63	Yes	T62,T21,T63	INOUT
IOR2	Yes	Yes	T62,T21,T63	Yes	T62,T21,T63	INOUT
IOR3	Yes	Yes	T62,T21,T63	Yes	T62,T21,T63	INOUT
IOR4	Yes	Yes	T62,T21,T22	Yes	T4,T62,T64	INOUT
IOR5	Yes	Yes	T31,T40,T35	Yes	T31,T24,T40	INOUT
IOR6	Yes	Yes	T31,T40,T212	Yes	T31,T24,T40	INOUT
IOR7	Yes	Yes	T31,T40,T212	Yes	T31,T24,T40	INOUT
IOR10	Yes	Yes	T31,T40,T212	Yes	T31,T24,T40	INOUT
IOR11	Yes	Yes	T31,T40,T212	Yes	T31,T40,T212	INOUT
IOR12	Yes	Yes	T31,T40,T212	Yes	T31,T40,T212	INOUT
IOR13	Yes	Yes	T1,T107,T31	Yes	T1,T107,T31	INOUT

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	789	1	0	0.00
CONT_ASSIGN	800	1	0	0.00
CONT_ASSIGN	825	1	0	0.00
CONT_ASSIGN	832	1	0	0.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	842	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	854	1	0	0.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1024	1	1	100.00
CONT_ASSIGN	1025	1	1	100.00
CONT_ASSIGN	1032	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
CONT_ASSIGN	1050	1	1	100.00
CONT_ASSIGN	1051	1	1	100.00
CONT_ASSIGN	1052	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00
CONT_ASSIGN	1057	1	1	100.00
CONT_ASSIGN	1058	1	1	100.00
CONT_ASSIGN	1059	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
214	1	1
215	1	1
789	0	1
800	0	1
825	0	1
832	0	1
839	1	1
842	1	1
848	1	1
850	1	1
854	0	1
857	1	1
1022	1	1
1023	1	1
1024	1	1
1025	1	1
1032	1	1
1049	1	1
1050	1	1
1051	1	1
1052	1	1
1056	1	1
1057	1	1
1058	1	1
1059	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T68,T126

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	66	64	96.97
Total Bits	132	130	98.48
Total Bits 0->1	66	66	100.00
Total Bits 1->0	66	64	96.97

Ports	66	64	96.97
Port Bits	132	130	98.48
Port Bits 0->1	66	66	100.00
Port Bits 1->0	66	64	96.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
POR_N	Yes	Yes	T21,T22,T23	Yes	T4,T5,T6	INOUT
USB_P	Yes	Yes	T32,T33,T37	Yes	T32,T33,T37	INOUT
USB_N	Yes	Yes	T32,T33,T37	Yes	T32,T33,T37	INOUT
CC1	No	No		Yes	T24,T25,T26	INOUT
CC2	No	No		Yes	T24,T25,T26	INOUT
FLASH_TEST_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INOUT
SPI_HOST_D1	Yes	Yes	T27,T28,T29	Yes	T27,T24,T28	INOUT
SPI_HOST_D2	Yes	Yes	T27,T188,T189	Yes	T27,T188,T189	INOUT
SPI_HOST_D3	Yes	Yes	T27,T188,T189	Yes	T27,T188,T189	INOUT
SPI_HOST_CLK	Yes	Yes	T27,T28,T29	Yes	T27,T24,T28	INOUT
SPI_HOST_CS_L	Yes	Yes	T27,T75,T28	Yes	T27,T75,T24	INOUT
SPI_DEV_D0	Yes	Yes	T27,T28,T83	Yes	T27,T28,T83	INOUT
SPI_DEV_D1	Yes	Yes	T27,T28,T83	Yes	T27,T28,T83	INOUT
SPI_DEV_D2	Yes	Yes	T27,T188,T189	Yes	T27,T188,T25	INOUT
SPI_DEV_D3	Yes	Yes	T27,T188,T189	Yes	T27,T188,T189	INOUT
SPI_DEV_CLK	Yes	Yes	T27,T28,T83	Yes	T27,T24,T28	INOUT
SPI_DEV_CS_L	Yes	Yes	T27,T24,T28	Yes	T27,T24,T28	INOUT
IOR8	Yes	Yes	T107,T202,T34	Yes	T107,T3,T202	INOUT
IOR9	Yes	Yes	T202,T34,T35	Yes	T50,T107,T3	INOUT
IOA0	Yes	Yes	T30,T31,T2	Yes	T30,T31,T24	INOUT
IOA1	Yes	Yes	T30,T31,T2	Yes	T30,T31,T2	INOUT
IOA2	Yes	Yes	T31,T2,T208	Yes	T31,T2,T208	INOUT
IOA3	Yes	Yes	T31,T2,T13	Yes	T31,T24,T2	INOUT
IOA4	Yes	Yes	T31,T2,T207	Yes	T31,T2,T207	INOUT
IOA5	Yes	Yes	T31,T2,T207	Yes	T31,T2,T207	INOUT
IOA6	Yes	Yes	T31,T2,T13	Yes	T31,T2,T13	INOUT
IOA7	Yes	Yes	T19,T31,T2	Yes	T19,T31,T2	INOUT
IOA8	Yes	Yes	T19,T31,T2	Yes	T19,T31,T2	INOUT
IOB0	Yes	Yes	T48,T49,T46	Yes	T24,T48,T26	INOUT
IOB1	Yes	Yes	T48,T49,T46	Yes	T48,T25,T49	INOUT
IOB2	Yes	Yes	T46,T43,T44	Yes	T25,T46,T43	INOUT
IOB3	Yes	Yes	T107,T48,T202	Yes	T107,T48,T202	INOUT
IOB4	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	INOUT
IOB5	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	INOUT
IOB6	Yes	Yes	T107,T31,T202	Yes	T107,T31,T202	INOUT
IOB7	Yes	Yes	T1,T31,T10	Yes	T50,T1,T31	INOUT
IOB8	Yes	Yes	T107,T31,T202	Yes	T107,T31,T202	INOUT
IOB9	Yes	Yes	T216,T31,T342	Yes	T216,T31,T24	INOUT
IOB10	Yes	Yes	T216,T31,T218	Yes	T216,T31,T218	INOUT
IOB11	Yes	Yes	T31,T218,T208	Yes	T31,T218,T208	INOUT
IOB12	Yes	Yes	T31,T218,T208	Yes	T31,T218,T208	INOUT
IOC0	Yes	Yes	T59,T60,T61	Yes	T83,T152,T269	INOUT
IOC1	Yes	Yes	T83,T152,T219	Yes	T83,T152,T219	INOUT
IOC2	Yes	Yes	T83,T152,T219	Yes	T24,T83,T152	INOUT
IOC3	Yes	Yes	T124,T220,T354	Yes	T124,T220,T354	INOUT
IOC4	Yes	Yes	T124,T56,T57	Yes	T124,T56,T57	INOUT
IOC5	Yes	Yes	T62,T73,T74	Yes	T62,T73,T74	INOUT
IOC6	Yes	Yes	T4,T64,T124	Yes	T4,T64,T124	INOUT
IOC7	Yes	Yes	T107,T202,T34	Yes	T32,T107,T33	INOUT
IOC8	Yes	Yes	T62,T73,T74	Yes	T62,T73,T74	INOUT
IOC9	Yes	Yes	T50,T107,T31	Yes	T50,T107,T31	INOUT
IOC10	Yes	Yes	T31,T218,T208	Yes	T31,T218,T208	INOUT
IOC11	Yes	Yes	T31,T218,T208	Yes	T31,T218,T208	INOUT
IOC12	Yes	Yes	T31,T218,T208	Yes	T31,T24,T218	INOUT
IOR0	Yes	Yes	T62,T21,T63	Yes	T62,T21,T63	INOUT
IOR1	Yes	Yes	T62,T21,T63	Yes	T62,T21,T63	INOUT
IOR2	Yes	Yes	T62,T21,T63	Yes	T62,T21,T63	INOUT
IOR3	Yes	Yes	T62,T21,T63	Yes	T62,T21,T63	INOUT
IOR4	Yes	Yes	T62,T21,T22	Yes	T4,T62,T64	INOUT
IOR5	Yes	Yes	T31,T40,T35	Yes	T31,T24,T40	INOUT
IOR6	Yes	Yes	T31,T40,T212	Yes	T31,T24,T40	INOUT
IOR7	Yes	Yes	T31,T40,T212	Yes	T31,T24,T40	INOUT
IOR10	Yes	Yes	T31,T40,T212	Yes	T31,T24,T40	INOUT
IOR11	Yes	Yes	T31,T40,T212	Yes	T31,T40,T212	INOUT
IOR12	Yes	Yes	T31,T40,T212	Yes	T31,T40,T212	INOUT
IOR13	Yes	Yes	T1,T107,T31	Yes	T1,T107,T31	INOUT