Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3516472	1			T73	5824		T74	88		T78	339
values[2]	714947	1			T73	1090		T74	20		T78	88
values[3]	97246	1			T73	85		T74	15		T125	48
values[4]	50205	1			T73	20		T74	1		T125	25
values[5]	33982	1			T73	17		T125	19		T548	8
values[6]	25933	1			T73	10		T125	13		T548	8
values[7]	21103	1			T125	16		T548	8		T836	18
values[8]	18115	1			T125	20		T548	8		T836	18
values[9]	16040	1			T125	13		T548	8		T836	18
values[10]	14662	1			T125	17		T548	8		T836	18
values[11]	13675	1			T125	12		T548	8		T836	19
values[12]	12769	1			T125	13		T548	8		T836	19
values[13]	12124	1			T125	2		T548	8		T836	18
values[14]	11553	1			T125	2		T548	8		T836	18
values[15]	11068	1			T548	8		T836	18		T553	7
values[16]	10740	1			T548	9		T836	18		T553	7
values[17]	10408	1			T548	8		T836	18		T553	7
values[18]	9809	1			T548	8		T836	18		T553	8
values[19]	9341	1			T548	8		T836	18		T553	7
values[20]	9104	1			T548	8		T836	19		T553	7
values[21]	8985	1			T548	9		T836	19		T553	7
values[22]	8601	1			T548	9		T836	18		T553	7
values[23]	8564	1			T548	8		T836	18		T553	7
values[24]	8080	1			T548	8		T836	19		T553	7
values[25]	7941	1			T548	8		T836	18		T553	8
values[26]	7710	1			T548	9		T836	19		T553	7
values[27]	7453	1			T548	8		T836	18		T553	7
values[28]	7038	1			T548	8		T836	19		T553	8
values[29]	6309	1			T548	8		T836	18		T553	7
values[30]	5990	1			T548	9		T836	18		T553	7
values[31]	5561	1			T548	8		T836	18		T553	7
values[32]	5044	1			T548	8		T836	18		T553	7
values[33]	4716	1			T548	8		T836	18		T553	7
values[34]	4500	1			T548	8		T836	18		T553	7
values[35]	4269	1			T548	8		T836	19		T553	7
values[36]	4123	1			T548	8		T836	18		T553	7
values[37]	3853	1			T548	8		T836	18		T553	7
values[38]	3731	1			T548	9		T836	18		T553	7
values[39]	3540	1			T548	8		T836	18		T553	7
values[40]	3384	1			T548	8		T836	18		T553	7
values[41]	3289	1			T548	8		T836	18		T553	7
values[42]	3358	1			T548	8		T836	18		T553	7
values[43]	3177	1			T548	8		T836	18		T553	7
values[44]	3058	1			T548	9		T836	18		T553	7
values[45]	2997	1			T548	8		T836	18		T553	9
values[46]	2971	1			T548	8		T836	18		T553	7
values[47]	2960	1			T548	8		T836	18		T553	7
values[48]	2995	1			T548	8		T836	18		T553	7
values[49]	2986	1			T548	8		T836	18		T553	7
values[50]	2872	1			T548	8		T836	18		T553	7
values[51]	2734	1			T548	8		T836	18		T553	7
values[52]	2671	1			T548	8		T836	18		T553	9
values[53]	2689	1			T548	8		T836	18		T553	7
values[54]	2743	1			T548	8		T836	18		T553	7
values[55]	2626	1			T548	8		T836	18		T553	7
values[56]	2585	1			T548	8		T836	18		T553	7
values[57]	2539	1			T548	8		T836	18		T553	7
values[58]	2484	1			T548	8		T836	18		T553	7
values[59]	2481	1			T548	8		T836	18		T553	7
values[60]	2413	1			T548	8		T836	18		T553	7
values[61]	2782	1			T548	8		T836	19		T553	7
values[62]	4367	1			T548	8		T836	18		T553	7
values[63]	16069	1			T548	9		T836	149		T553	141
values[64]	226951	1			T548	1504		T836	3417		T553	1139

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4539562	1			T73	8336		T74	48		T78	397
values[2]	758553	1			T73	1206		T74	22		T78	110
values[3]	71727	1			T73	93		T74	14		T78	2
values[4]	14122	1			T73	9		T74	8		T262	1
values[5]	5915	1			T73	5		T74	1		T548	12
values[6]	3625	1			T73	8		T548	4		T557	4
values[7]	2602	1			T73	5		T548	3		T557	2
values[8]	2121	1			T73	4		T548	1		T836	2
values[9]	1771	1			T73	7		T836	2		T562	1
values[10]	1545	1			T73	1		T836	2		T562	1
values[11]	1410	1			T73	4		T836	2		T562	1
values[12]	1307	1			T73	2		T836	2		T562	1
values[13]	1272	1			T836	2		T562	1		T555	1
values[14]	1047	1			T836	2		T562	1		T555	1
values[15]	951	1			T836	2		T562	1		T555	1
values[16]	978	1			T836	2		T562	1		T555	1
values[17]	958	1			T836	2		T562	1		T555	1
values[18]	1001	1			T836	2		T562	1		T555	1
values[19]	981	1			T836	2		T562	1		T555	1
values[20]	894	1			T836	2		T562	1		T555	1
values[21]	817	1			T836	2		T562	1		T555	1
values[22]	708	1			T836	2		T562	1		T555	1
values[23]	639	1			T836	2		T562	1		T555	1
values[24]	649	1			T836	2		T562	1		T555	1
values[25]	615	1			T836	2		T562	1		T555	1
values[26]	585	1			T836	2		T562	1		T555	1
values[27]	581	1			T836	2		T562	1		T555	1
values[28]	559	1			T836	2		T562	1		T555	1
values[29]	604	1			T836	2		T562	1		T555	1
values[30]	567	1			T836	2		T562	1		T555	1
values[31]	525	1			T836	2		T562	1		T555	1
values[32]	529	1			T836	2		T562	1		T555	1
values[33]	504	1			T836	2		T562	1		T555	1
values[34]	512	1			T836	2		T562	1		T555	1
values[35]	474	1			T836	2		T562	1		T555	1
values[36]	469	1			T836	2		T562	1		T555	1
values[37]	469	1			T836	2		T562	1		T555	1
values[38]	441	1			T836	2		T562	1		T555	1
values[39]	430	1			T836	2		T562	1		T555	1
values[40]	419	1			T836	2		T562	1		T555	2
values[41]	405	1			T836	2		T562	1		T555	1
values[42]	390	1			T836	2		T562	1		T555	1
values[43]	379	1			T836	2		T562	1		T555	1
values[44]	427	1			T836	2		T562	1		T555	1
values[45]	426	1			T836	2		T562	1		T555	1
values[46]	376	1			T836	2		T562	1		T555	1
values[47]	406	1			T836	2		T562	1		T555	1
values[48]	374	1			T836	2		T562	1		T555	1
values[49]	361	1			T836	2		T562	1		T555	1
values[50]	349	1			T836	2		T562	1		T555	1
values[51]	350	1			T836	2		T562	1		T555	1
values[52]	369	1			T836	2		T562	1		T555	1
values[53]	345	1			T836	2		T562	1		T555	1
values[54]	326	1			T836	2		T562	2		T555	1
values[55]	323	1			T836	2		T562	1		T555	1
values[56]	331	1			T836	2		T562	1		T555	1
values[57]	314	1			T836	2		T562	1		T555	1
values[58]	332	1			T836	2		T562	1		T555	1
values[59]	338	1			T836	2		T562	1		T555	1
values[60]	310	1			T836	2		T562	1		T555	1
values[61]	378	1			T836	2		T562	1		T555	1
values[62]	573	1			T836	2		T562	1		T555	1
values[63]	2590	1			T836	39		T562	23		T555	1
values[64]	23797	1			T836	323		T562	179		T555	220

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	523034	1			T73	267		T74	1		T78	3
values[2]	2557817	1			T73	2462		T74	1		T78	338
values[3]	1098483	1			T73	3804		T74	67		T78	102
values[4]	132011	1			T73	96		T74	19		T125	69
values[5]	66790	1			T73	31		T74	4		T125	21
values[6]	44199	1			T73	23		T125	11		T262	15
values[7]	32432	1			T73	11		T125	9		T262	4
values[8]	26138	1			T73	13		T125	3		T548	8
values[9]	21757	1			T73	10		T125	1		T548	8
values[10]	18831	1			T73	10		T548	8		T836	19
values[11]	16984	1			T73	9		T548	8		T836	18
values[12]	15453	1			T73	7		T548	8		T836	18
values[13]	14556	1			T73	4		T548	8		T836	18
values[14]	13880	1			T73	9		T548	9		T836	18
values[15]	13272	1			T73	5		T548	8		T836	19
values[16]	12619	1			T73	2		T548	8		T836	18
values[17]	12326	1			T73	8		T548	8		T836	18
values[18]	11699	1			T73	8		T548	8		T836	18
values[19]	11439	1			T73	8		T548	8		T836	18
values[20]	10891	1			T73	6		T548	8		T836	18
values[21]	10300	1			T73	5		T548	8		T836	18
values[22]	10093	1			T73	2		T548	8		T836	18
values[23]	9918	1			T73	3		T548	8		T836	18
values[24]	9428	1			T73	2		T548	8		T836	18
values[25]	9069	1			T73	1		T548	8		T836	18
values[26]	8560	1			T73	2		T548	9		T836	18
values[27]	8446	1			T73	3		T548	8		T836	18
values[28]	7886	1			T73	2		T548	8		T836	18
values[29]	7599	1			T73	3		T548	8		T836	18
values[30]	7047	1			T73	10		T548	8		T836	19
values[31]	6589	1			T73	8		T548	8		T836	18
values[32]	6233	1			T73	1		T548	8		T836	19
values[33]	5812	1			T73	2		T548	8		T836	18
values[34]	5222	1			T73	2		T548	8		T836	19
values[35]	4817	1			T73	2		T548	9		T836	18
values[36]	4368	1			T73	2		T548	8		T836	18
values[37]	4167	1			T73	3		T548	8		T836	18
values[38]	4076	1			T73	1		T548	8		T836	18
values[39]	3912	1			T73	1		T548	8		T836	18
values[40]	3777	1			T73	1		T548	8		T836	19
values[41]	3667	1			T73	3		T548	8		T836	18
values[42]	3585	1			T73	1		T548	8		T836	18
values[43]	3508	1			T73	1		T548	8		T836	18
values[44]	3506	1			T73	4		T548	9		T836	18
values[45]	3309	1			T73	2		T548	8		T836	19
values[46]	3266	1			T73	3		T548	8		T836	18
values[47]	3322	1			T73	1		T548	8		T836	18
values[48]	3243	1			T73	6		T548	8		T836	18
values[49]	3122	1			T73	5		T548	9		T836	19
values[50]	3030	1			T73	2		T548	8		T836	18
values[51]	3107	1			T73	1		T548	9		T836	18
values[52]	3065	1			T548	8		T836	18		T553	7
values[53]	3079	1			T548	8		T836	18		T553	7
values[54]	3112	1			T548	8		T836	18		T553	7
values[55]	3093	1			T548	8		T836	18		T553	8
values[56]	2773	1			T548	8		T836	18		T553	7
values[57]	2664	1			T548	8		T836	18		T553	7
values[58]	2547	1			T548	8		T836	18		T553	7
values[59]	2671	1			T548	8		T836	18		T553	7
values[60]	2651	1			T548	8		T836	19		T553	7
values[61]	2858	1			T548	8		T836	18		T553	7
values[62]	4167	1			T548	8		T836	18		T553	7
values[63]	17079	1			T548	132		T836	20		T553	177
values[64]	216105	1			T548	1433		T836	3226		T553	981