Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2245298	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33371964

1

T4

7619

T5

15826

T6

11867

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24401061	1			T4	3494		T5	7203		T6	1784
values[0x0]	9484192	1			T4	4125		T5	8623		T6	10083
values[0x1]	1732009	1			T4	381		T5	1264		T6	87

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	632488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34984774

1

T4

8000

T5

17090

T6

11954

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16646597	1			T4	4000		T5	8546		T6	5978
valid_sources[0x01]	16646142	1			T4	4000		T5	8544		T6	5976
valid_sources[0x02]	37025	1			T67	2		T198	1		T75	47
valid_sources[0x03]	37505	1			T67	3		T76	2		T9	2
valid_sources[0x04]	37173	1			T67	1		T76	1		T198	1
valid_sources[0x05]	36331	1			T67	3		T198	1		T9	4
valid_sources[0x06]	37612	1			T67	1		T75	25		T143	71
valid_sources[0x07]	36750	1			T76	1		T9	1		T75	19
valid_sources[0x08]	36213	1			T67	1		T77	7		T75	29
valid_sources[0x09]	37592	1			T198	1		T9	1		T75	46
valid_sources[0x0a]	37530	1			T67	1		T198	1		T75	24
valid_sources[0x0b]	36777	1			T76	2		T75	79		T143	76
valid_sources[0x0c]	37142	1			T198	1		T75	34		T143	81
valid_sources[0x0d]	36315	1			T198	1		T75	20		T143	82
valid_sources[0x0e]	36704	1			T67	2		T198	1		T75	36
valid_sources[0x0f]	37639	1			T76	1		T199	39		T75	40
valid_sources[0x10]	37586	1			T76	1		T9	1		T75	47
valid_sources[0x11]	37640	1			T67	2		T76	3		T75	45
valid_sources[0x12]	38200	1			T67	2		T76	2		T75	21
valid_sources[0x13]	37756	1			T67	1		T198	1		T75	34
valid_sources[0x14]	40851	1			T67	1		T198	2		T9	1
valid_sources[0x15]	39615	1			T198	2		T75	26		T143	70
valid_sources[0x16]	37981	1			T67	1		T75	31		T143	121
valid_sources[0x17]	36516	1			T76	1		T75	24		T143	81
valid_sources[0x18]	37613	1			T67	1		T9	1		T75	36
valid_sources[0x19]	37739	1			T198	1		T9	1		T75	37
valid_sources[0x1a]	36756	1			T9	1		T75	29		T143	82
valid_sources[0x1b]	37061	1			T76	1		T198	2		T75	20
valid_sources[0x1c]	37741	1			T198	2		T75	19		T143	69
valid_sources[0x1d]	36482	1			T67	2		T76	3		T77	1
valid_sources[0x1e]	37132	1			T76	1		T198	2		T9	2
valid_sources[0x1f]	36613	1			T198	2		T75	20		T143	57
valid_sources[0x20]	36983	1			T76	2		T77	13		T75	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23693762

1

T4

3494

T5

7203

T6

1784

values[0x0]

all_enables

biggest_size

9438517

1

T4

4125

T5

8623

T6

10083

values[0x1]

all_enables

biggest_size

239685

1

T67

19

T76

21

T77

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2846706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

450423

1

T73

974

T74

23

T78

62

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1116322	1			T73	2316		T74	45		T78	144
values[0x0]	1065237	1			T73	2281		T74	42		T78	139
values[0x1]	1115570	1			T73	2431		T74	37		T78	144

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2203416	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1093713

1

T73

2355

T74

46

T78

152

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51805	1			T73	104		T78	9		T125	1
valid_sources[0x01]	51786	1			T73	93		T74	1		T78	9
valid_sources[0x02]	51979	1			T73	101		T74	1		T78	1
valid_sources[0x03]	51796	1			T73	119		T74	3		T125	6
valid_sources[0x04]	51488	1			T73	105		T125	2		T262	5
valid_sources[0x05]	52474	1			T73	106		T74	6		T262	4
valid_sources[0x06]	52207	1			T73	104		T74	4		T78	14
valid_sources[0x07]	51792	1			T73	112		T74	1		T78	3
valid_sources[0x08]	51100	1			T73	152		T74	1		T78	5
valid_sources[0x09]	51827	1			T73	143		T74	3		T78	5
valid_sources[0x0a]	52124	1			T73	119		T74	1		T78	17
valid_sources[0x0b]	52118	1			T73	102		T74	1		T78	1
valid_sources[0x0c]	50158	1			T73	104		T78	14		T125	4
valid_sources[0x0d]	50686	1			T73	91		T74	2		T125	5
valid_sources[0x0e]	51344	1			T73	92		T125	3		T262	1
valid_sources[0x0f]	51938	1			T73	80		T74	4		T125	4
valid_sources[0x10]	52224	1			T73	125		T74	2		T78	1
valid_sources[0x11]	51153	1			T73	122		T74	5		T78	26
valid_sources[0x12]	49753	1			T73	113		T78	2		T125	4
valid_sources[0x13]	51976	1			T73	96		T74	4		T125	2
valid_sources[0x14]	49949	1			T73	82		T74	4		T125	6
valid_sources[0x15]	51665	1			T73	96		T74	3		T78	3
valid_sources[0x16]	52204	1			T73	125		T74	1		T78	2
valid_sources[0x17]	52646	1			T73	136		T74	3		T78	9
valid_sources[0x18]	50056	1			T73	140		T74	3		T78	14
valid_sources[0x19]	50712	1			T73	108		T74	6		T78	4
valid_sources[0x1a]	50994	1			T73	131		T74	1		T78	9
valid_sources[0x1b]	51657	1			T73	115		T74	1		T125	1
valid_sources[0x1c]	51507	1			T73	89		T125	2		T262	5
valid_sources[0x1d]	51381	1			T73	138		T74	5		T125	2
valid_sources[0x1e]	51093	1			T73	94		T74	1		T78	5
valid_sources[0x1f]	52016	1			T73	98		T125	7		T558	2
valid_sources[0x20]	51616	1			T73	90		T74	2		T78	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47428

1

T73

100

T74

1

T78

5

values[0x0]

all_enables

biggest_size

355864

1

T73

761

T74

19

T78

50

values[0x1]

all_enables

biggest_size

47131

1

T73

113

T74

3

T78

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3041236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

495871

1

T73

1357

T74

13

T78

72

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1208982	1			T73	3295		T74	36		T78	170
values[0x0]	1118918	1			T73	3125		T74	24		T78	163
values[0x1]	1209207	1			T73	3247		T74	33		T78	176

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2334536	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1202571

1

T73

3268

T74

34

T78

186

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55542	1			T73	114		T78	4		T125	7
valid_sources[0x01]	55152	1			T73	181		T74	1		T78	6
valid_sources[0x02]	54713	1			T73	139		T74	4		T125	1
valid_sources[0x03]	54929	1			T73	146		T74	3		T125	3
valid_sources[0x04]	57140	1			T73	143		T74	1		T78	5
valid_sources[0x05]	56135	1			T73	161		T78	13		T125	5
valid_sources[0x06]	55527	1			T73	134		T74	1		T78	24
valid_sources[0x07]	56029	1			T73	190		T125	1		T262	2
valid_sources[0x08]	55249	1			T73	185		T74	3		T125	3
valid_sources[0x09]	54491	1			T73	156		T125	3		T262	1
valid_sources[0x0a]	55885	1			T73	111		T78	15		T125	1
valid_sources[0x0b]	55457	1			T73	147		T74	1		T78	8
valid_sources[0x0c]	55165	1			T73	149		T74	1		T78	3
valid_sources[0x0d]	54347	1			T73	173		T74	3		T78	5
valid_sources[0x0e]	54623	1			T73	146		T78	27		T125	1
valid_sources[0x0f]	55268	1			T73	179		T74	3		T78	17
valid_sources[0x10]	56316	1			T73	134		T74	1		T78	21
valid_sources[0x11]	56497	1			T73	179		T78	44		T262	2
valid_sources[0x12]	54961	1			T73	169		T78	20		T125	1
valid_sources[0x13]	55476	1			T73	186		T74	3		T78	8
valid_sources[0x14]	55397	1			T73	163		T74	1		T78	7
valid_sources[0x15]	56110	1			T73	138		T78	2		T125	2
valid_sources[0x16]	55365	1			T73	155		T74	1		T78	24
valid_sources[0x17]	55387	1			T73	167		T74	1		T125	1
valid_sources[0x18]	54350	1			T73	111		T74	1		T78	3
valid_sources[0x19]	55608	1			T73	100		T74	3		T78	8
valid_sources[0x1a]	56339	1			T73	156		T74	5		T78	3
valid_sources[0x1b]	55948	1			T73	162		T74	1		T78	12
valid_sources[0x1c]	55749	1			T73	143		T78	6		T125	2
valid_sources[0x1d]	54744	1			T73	121		T74	1		T78	18
valid_sources[0x1e]	54907	1			T73	140		T74	1		T125	2
valid_sources[0x1f]	56152	1			T73	161		T74	1		T78	8
valid_sources[0x20]	55692	1			T73	191		T74	2		T78	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51756

1

T73

136

T74

1

T78

6

values[0x0]

all_enables

biggest_size

392156

1

T73

1082

T74

10

T78

58

values[0x1]

all_enables

biggest_size

51959

1

T73

139

T74

2

T78

8

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2872407	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

454480

1

T73

922

T74

10

T78

63

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1125713	1			T73	2311		T74	32		T78	140
values[0x0]	1076480	1			T73	2214		T74	34		T78	151
values[0x1]	1124694	1			T73	2321		T74	26		T78	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2225084	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1101803

1

T73

2185

T74

23

T78

147

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52853	1			T73	80		T74	1		T78	5
valid_sources[0x01]	51896	1			T73	127		T74	3		T78	9
valid_sources[0x02]	52037	1			T73	101		T74	1		T78	4
valid_sources[0x03]	52392	1			T73	132		T78	7		T125	3
valid_sources[0x04]	52873	1			T73	84		T78	5		T125	3
valid_sources[0x05]	52714	1			T73	116		T74	2		T78	5
valid_sources[0x06]	51574	1			T73	94		T74	4		T78	12
valid_sources[0x07]	52172	1			T73	152		T78	10		T125	3
valid_sources[0x08]	51562	1			T73	125		T74	1		T78	10
valid_sources[0x09]	52003	1			T73	104		T78	11		T125	3
valid_sources[0x0a]	52063	1			T73	88		T74	2		T78	6
valid_sources[0x0b]	52364	1			T73	102		T74	3		T78	8
valid_sources[0x0c]	51795	1			T73	137		T74	1		T78	10
valid_sources[0x0d]	51380	1			T73	109		T74	1		T78	4
valid_sources[0x0e]	52063	1			T73	92		T78	6		T125	4
valid_sources[0x0f]	52823	1			T73	104		T74	1		T78	4
valid_sources[0x10]	51806	1			T73	107		T78	5		T125	2
valid_sources[0x11]	52500	1			T73	125		T74	2		T78	9
valid_sources[0x12]	51216	1			T73	88		T74	1		T78	9
valid_sources[0x13]	51895	1			T73	100		T78	8		T125	4
valid_sources[0x14]	50663	1			T73	142		T74	3		T78	5
valid_sources[0x15]	53259	1			T73	104		T74	1		T78	5
valid_sources[0x16]	52927	1			T73	112		T74	1		T78	6
valid_sources[0x17]	52536	1			T73	135		T78	7		T262	4
valid_sources[0x18]	51268	1			T73	114		T78	10		T125	6
valid_sources[0x19]	51393	1			T73	96		T74	1		T78	4
valid_sources[0x1a]	52298	1			T73	97		T74	1		T78	11
valid_sources[0x1b]	52566	1			T73	88		T74	2		T78	3
valid_sources[0x1c]	52004	1			T73	82		T74	2		T78	5
valid_sources[0x1d]	52231	1			T73	129		T74	1		T78	8
valid_sources[0x1e]	51828	1			T73	115		T74	6		T78	4
valid_sources[0x1f]	52763	1			T73	64		T74	1		T78	11
valid_sources[0x20]	51734	1			T73	119		T74	5		T78	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47686

1

T73

99

T74

2

T78

5

values[0x0]

all_enables

biggest_size

359400

1

T73

722

T74

8

T78

52

values[0x1]

all_enables

biggest_size

47394

1

T73

101

T78

6

T125

6