Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478410453	54342575	0	0
DepthKnown_A	478410453	478304986	0	0
RvalidKnown_A	478410453	478304986	0	0
WreadyKnown_A	478410453	478304986	0	0
gen_passthru_fifo.paramCheckPass	997	997	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	54342575	0	0
T1	619471	84402	0	0
T4	146788	22453	0	0
T5	256527	32789	0	0
T6	412264	159605	0	0
T17	210481	21986	0	0
T42	499934	70102	0	0
T61	250211	32585	0	0
T70	157152	3461	0	0
T82	240952	25964	0	0
T83	88839	9744	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	997	997	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478410453	41936727	0	0
DepthKnown_A	478410453	478304986	0	0
RvalidKnown_A	478410453	478304986	0	0
WreadyKnown_A	478410453	478304986	0	0
gen_passthru_fifo.paramCheckPass	997	997	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	41936727	0	0
T1	619471	60792	0	0
T4	146788	15857	0	0
T5	256527	23873	0	0
T6	412264	80172	0	0
T17	210481	18140	0	0
T42	499934	63335	0	0
T61	250211	23199	0	0
T70	157152	1868	0	0
T82	240952	22117	0	0
T83	88839	7456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	997	997	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478410453	39627579	0	0
DepthKnown_A	478410453	478304986	0	0
RvalidKnown_A	478410453	478304986	0	0
WreadyKnown_A	478410453	478304986	0	0
gen_passthru_fifo.paramCheckPass	997	997	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	39627579	0	0
T1	619471	38246	0	0
T4	146788	8271	0	0
T5	256527	17479	0	0
T6	412264	12949	0	0
T17	210481	20054	0	0
T42	499934	59720	0	0
T61	250211	16662	0	0
T70	157152	459	0	0
T82	240952	22916	0	0
T83	88839	8270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	997	997	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478410453	33315121	0	0
DepthKnown_A	478410453	478304986	0	0
RvalidKnown_A	478410453	478304986	0	0
WreadyKnown_A	478410453	478304986	0	0
gen_passthru_fifo.paramCheckPass	997	997	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	33315121	0	0
T1	619471	36924	0	0
T4	146788	8000	0	0
T5	256527	17090	0	0
T6	412264	11954	0	0
T17	210481	19854	0	0
T42	499934	59319	0	0
T61	250211	16268	0	0
T70	157152	351	0	0
T82	240952	22715	0	0
T83	88839	7910	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	478304986	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	997	997	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	546788027	88845	0	0
DepthKnown_A	546788027	546670686	0	0
RvalidKnown_A	546788027	546670686	0	0
WreadyKnown_A	546788027	546670686	0	0
gen_passthru_fifo.paramCheckPass	2887	2887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	88845	0	0
T1	619471	122	0	0
T4	146788	26	0	0
T5	256527	153	0	0
T6	412264	73	0	0
T17	210481	53	0	0
T42	499934	39	0	0
T61	250211	151	0	0
T70	157152	8	0	0
T82	240952	53	0	0
T83	88839	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2887	2887	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	546788027	92651	0	0
DepthKnown_A	546788027	546670686	0	0
RvalidKnown_A	546788027	546670686	0	0
WreadyKnown_A	546788027	546670686	0	0
gen_passthru_fifo.paramCheckPass	2887	2887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	92651	0	0
T1	619471	122	0	0
T4	146788	26	0	0
T5	256527	153	0	0
T6	412264	73	0	0
T17	210481	53	0	0
T42	499934	39	0	0
T61	250211	151	0	0
T70	157152	8	0	0
T82	240952	53	0	0
T83	88839	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2887	2887	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	546788027	51769	0	0
DepthKnown_A	546788027	546670686	0	0
RvalidKnown_A	546788027	546670686	0	0
WreadyKnown_A	546788027	546670686	0	0
gen_passthru_fifo.paramCheckPass	2887	2887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	51769	0	0
T1	619471	104	0	0
T4	146788	23	0	0
T5	256527	95	0	0
T6	412264	69	0	0
T17	210481	52	0	0
T42	499934	37	0	0
T61	250211	95	0	0
T70	157152	8	0	0
T82	240952	52	0	0
T83	88839	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2887	2887	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	546788027	51767	0	0
DepthKnown_A	546788027	546670686	0	0
RvalidKnown_A	546788027	546670686	0	0
WreadyKnown_A	546788027	546670686	0	0
gen_passthru_fifo.paramCheckPass	2887	2887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	51767	0	0
T1	619471	104	0	0
T4	146788	23	0	0
T5	256527	95	0	0
T6	412264	69	0	0
T17	210481	52	0	0
T42	499934	37	0	0
T61	250211	95	0	0
T70	157152	8	0	0
T82	240952	52	0	0
T83	88839	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2887	2887	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	546788027	37076	0	0
DepthKnown_A	546788027	546670686	0	0
RvalidKnown_A	546788027	546670686	0	0
WreadyKnown_A	546788027	546670686	0	0
gen_passthru_fifo.paramCheckPass	2887	2887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	37076	0	0
T1	619471	18	0	0
T4	146788	3	0	0
T5	256527	58	0	0
T6	412264	4	0	0
T17	210481	1	0	0
T42	499934	2	0	0
T61	250211	56	0	0
T70	157152	0	0	0
T82	240952	1	0	0
T83	88839	1	0	0
T101	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2887	2887	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	546788027	40884	0	0
DepthKnown_A	546788027	546670686	0	0
RvalidKnown_A	546788027	546670686	0	0
WreadyKnown_A	546788027	546670686	0	0
gen_passthru_fifo.paramCheckPass	2887	2887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	40884	0	0
T1	619471	18	0	0
T4	146788	3	0	0
T5	256527	58	0	0
T6	412264	4	0	0
T17	210481	1	0	0
T42	499934	2	0	0
T61	250211	56	0	0
T70	157152	0	0	0
T82	240952	1	0	0
T83	88839	1	0	0
T101	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	546788027	546670686	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2887	2887	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0