Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.36	89.96		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T73,T74,T262	Yes	T73,T74,T78	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T73,T125,T262	Yes	T73,T125,T262	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T62,T19,T66	Yes	T62,T19,T66	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T62,T19,T66	Yes	T62,T19,T66	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T67,T76,T77	Yes	T67,T76,T77	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T67,T77,T199	Yes	T67,T77,T199	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T67,T77,T199	Yes	T67,T77,T199	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T61,T62,T224	Yes	T61,T62,T224	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T55,T66,T67	Yes	T55,T66,T67	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T55,T66,T67	Yes	T55,T66,T67	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T55,T66,T67	Yes	T55,T66,T67	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T55,T66,T67	Yes	T55,T66,T67	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T55,T67,T63	Yes	T55,T67,T63	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T55,T66,T67	Yes	T55,T66,T67	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T55,*T66,*T67	Yes	T55,T66,T67	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T55,T66,T67	Yes	T55,T66,T67	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T9,T73,T74	Yes	T9,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T9,T73,T74	Yes	T9,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T9,T73,T74	Yes	T9,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T9,T73,T74	Yes	T9,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T9,T73,T74	Yes	T9,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T9,T73,T74	Yes	T9,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T9,T73,T74	Yes	T9,T73,T74	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T9,T73,T74	Yes	T9,T73,T74	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T75,T78	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T73,T78,T125	Yes	T73,T74,T78	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T73,T74	Yes	T9,T73,T75	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T9,T73,T74	Yes	T9,T73,T74	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T73,T78,T125	Yes	T73,T78,T125	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T9,T73,T78	Yes	T9,T73,T74	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T74,T75	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T9,*T73,*T78	Yes	T9,T73,T74	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T9,T73,T74	Yes	T9,T73,T74	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T66,T271,T272	Yes	T66,T271,T272	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T66,T271,T272	Yes	T66,T271,T272	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T66,T271,T272	Yes	T66,T271,T272	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T66,T271,T272	Yes	T66,T271,T272	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T66,T271,T272	Yes	T66,T271,T272	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T66,*T271,*T272	Yes	T66,T271,T272	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T66,T271,T272	Yes	T66,T271,T272	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T42	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T66,T271,T272	Yes	T66,T271,T272	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T66,T271,T272	Yes	T66,T271,T272	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T42	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T66,*T271,*T272	Yes	T66,T271,T272	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T75,T78	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T6,T42	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T66,T271,T272	Yes	T66,T271,T272	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T240,T437,T56	Yes	T240,T437,T56	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T240,T437,T56	Yes	T240,T437,T56	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T240,T437,T56	Yes	T240,T437,T56	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T9,*T73,*T74	Yes	T9,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T240,T437,T56	Yes	T240,T437,T56	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T240,T437,T56	Yes	T240,T437,T56	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T240,T283,T438	Yes	T240,T283,T438	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T73,T74	Yes	T56,T57,T58	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T240,T283,T438	Yes	T240,T56,T57	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T9,*T73,*T78	Yes	T9,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T74,T75	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T240,*T437,*T283	Yes	T240,T437,T283	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T240,T437,T56	Yes	T240,T437,T56	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T76	Yes	T66,T67,T76	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T67,T76,T77	Yes	T67,T76,T77	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T5,T61,T170	Yes	T5,T61,T170	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T66,*T67,*T76	Yes	T66,T67,T76	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T258,T160,T156	Yes	T258,T160,T156	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T258,T160,T156	Yes	T258,T160,T156	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T258,T160,T156	Yes	T258,T160,T156	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T258,T160,T156	Yes	T258,T160,T156	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T258,T160,T156	Yes	T258,T160,T156	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T258,T160,T156	Yes	T258,T160,T156	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T78	Yes	T73,T74,T78	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T23,T186,T189	Yes	T23,T186,T189	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T258,T160,T156	Yes	T258,T160,T156	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T258,T160,T156	Yes	T258,T160,T156	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T258,T160,T156	Yes	T258,T160,T156	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T78	Yes	T73,T74,T78	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T258,T160,T156	Yes	T258,T160,T156	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T56,T57,T403	Yes	T56,T57,T403	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T56,T57,T43	Yes	T56,T57,T43	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T56,T57,T403	Yes	T56,T57,T403	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T56,T57,T403	Yes	T56,T57,T403	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T56,T57,T43	Yes	T56,T57,T43	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T56,T57,T403	Yes	T56,T57,T403	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T78	Yes	T73,T74,T78	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T56,T57,T403	Yes	T56,T57,T403	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T56,T57,T403	Yes	T56,T57,T403	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T43,T98,T153	Yes	T43,T98,T153	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T403,T43,T98	Yes	T56,T57,T403	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T43,T98,T153	Yes	T43,T98,T153	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T73,*T78,*T125	Yes	T73,T74,T78	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T403,*T43,*T98	Yes	T403,T43,T98	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T56,T57,T403	Yes	T56,T57,T403	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T78	Yes	T73,T74,T78	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	INPUT
tl_usbdev_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T28,T29,T33	Yes	T28,T29,T33	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T28,T29,T33	Yes	T28,T29,T33	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T78,T125	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T73,*T78,*T125	Yes	T73,T74,T78	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T1,*T28,*T29	Yes	T1,T28,T29	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T42	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T42	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T76,*T9,T73	Yes	T76,T9,T73	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T73,T78,T125	Yes	T73,T74,T78	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T76,*T9,T73	Yes	T76,T9,T73	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T76,T9,T73	Yes	T76,T9,T73	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T42	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T111,T804,T366	Yes	T111,T804,T366	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	INPUT
tl_hmac_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	INPUT
tl_hmac_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T74,T75	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T53,*T19,*T269	Yes	T53,T19,T269	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T53,T19,T269	Yes	T53,T19,T269	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T42,T83,T442	Yes	T42,T83,T442	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T83,T442	Yes	T42,T83,T442	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T42,T83,T442	Yes	T42,T83,T442	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T42,T83,T442	Yes	T42,T83,T442	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T42,T83,T442	Yes	T42,T83,T442	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T83,T442,T414	Yes	T83,T442,T414	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T42,T83,T442	Yes	T42,T83,T442	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T42,T83,T442	Yes	T42,T83,T442	INPUT
tl_kmac_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T42,T83,T442	Yes	T42,T83,T442	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T83,T442	Yes	T42,T83,T442	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T42,T83,T442	Yes	T83,T442,T363	INPUT
tl_kmac_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T78,T125	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T42,*T83,*T442	Yes	T83,T442,T228	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T42,T83,T442	Yes	T42,T83,T442	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T67,*T73,*T78	Yes	T67,T73,T78	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	INPUT
tl_aes_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T74,T75	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	INPUT
tl_aes_i.d_sink	Yes	Yes	T73,T78,T125	Yes	T73,T74,T78	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T67,*T73,*T78	Yes	T67,T73,T78	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T74,T75	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T102,*T801,*T802	Yes	T102,T801,T802	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T102,T801,T802	Yes	T102,T801,T802	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T75,T78	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T73,T78,T125	Yes	T73,T74,T78	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T75,T78	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T42,*T19,*T269	Yes	T42,T53,T19	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T42,T182,T269	Yes	T42,T182,T269	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T67,*T76,*T9	Yes	T67,T76,T9	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T74,T75	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T42,T182,T269	Yes	T42,T182,T269	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T78,T125	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T67,*T76,*T9	Yes	T67,T76,T9	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T42,*T182,*T269	Yes	T42,T182,T269	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T73,T75,T125	Yes	T73,T75,T125	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T75,T78	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T42,*T269,*T108	Yes	T42,T269,T108	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	INPUT
tl_edn1_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	INPUT
tl_edn1_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T42,*T269,*T108	Yes	T42,T269,T108	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T42,T269,T108	Yes	T42,T269,T108	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T78	Yes	T73,T74,T78	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T73,T78,T125	Yes	T73,T78,T125	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T73,*T78,*T125	Yes	T73,T78,T125	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T73,T75,T78	Yes	T73,T75,T78	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_otbn_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T77,*T198,*T199	Yes	T77,T198,T199	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	INPUT
tl_otbn_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T75,T78	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	INPUT
tl_otbn_i.d_sink	Yes	Yes	T73,T78,T125	Yes	T73,T78,T125	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T77,*T198,*T199	Yes	T77,T198,T199	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T53,*T19,*T54	Yes	T53,T19,T54	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T42,T53,T19	Yes	T42,T53,T19	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T53,T19	Yes	T42,T53,T19	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T42,T53,T19	Yes	T42,T53,T19	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T42,T225,T108	Yes	T42,T225,T108	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T42,T53,T19	Yes	T42,T53,T19	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T42,T53,T19	Yes	T42,T53,T19	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T42,T53,T19	Yes	T42,T53,T19	INPUT
tl_keymgr_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T42,T225,T108	Yes	T42,T225,T108	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T53,T19	Yes	T42,T53,T19	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T42,T53,T19	Yes	T42,T53,T19	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T76,*T9,*T73	Yes	T76,T9,T73	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T42,*T53,*T19	Yes	T42,T53,T19	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T42,T53,T19	Yes	T42,T53,T19	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T271,*T273,*T9	Yes	T271,T273,T9	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T9,T73,T74	Yes	T9,T73,T74	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T61	Yes	T4,T5,T61	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T5,T61	Yes	T4,T5,T61	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T9,*T73,*T78	Yes	T271,T273,T9	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T5,T6,T42	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T78	Yes	T73,T74,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T178,T324,T325	Yes	T178,T324,T325	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T51,T112	Yes	T53,T19,T54	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T19,T51,T112	Yes	T53,T19,T54	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T78	Yes	T73,T74,T78	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T112,*T174,*T178	Yes	T377,T112,T426	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T53,T19,T54	Yes	T53,T19,T54	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T42	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T73,T74,T78	Yes	T73,T74,T78	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range