Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : pwrmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.57 99.57

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pwrmgr_aon 99.57 99.57



Module Instance : tb.dut.top_earlgrey.u_pwrmgr_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.57 99.57


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.57 99.57


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.36 89.96 90.10 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : pwrmgr
TotalCoveredPercent
Totals 84 83 98.81
Total Bits 462 460 99.57
Total Bits 0->1 231 230 99.57
Total Bits 1->0 231 230 99.57

Ports 84 83 98.81
Port Bits 462 460 99.57
Port Bits 0->1 231 230 99.57
Port Bits 1->0 231 230 99.57

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_slow_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_slow_ni Yes Yes T6,T18,T19 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T6,T18,T19 Yes T4,T5,T6 INPUT
rst_main_ni Yes Yes T6,T1,T105 Yes T4,T5,T6 INPUT
clk_lc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_lc_ni Yes Yes T5,T6,T42 Yes T4,T5,T6 INPUT
clk_esc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_esc_ni Yes Yes T5,T6,T42 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T1,T105 Yes T4,T1,T105 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T1,T105 Yes T4,T1,T105 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[6:0] Yes Yes *T73,*T74,*T75 Yes T73,T74,T75 INPUT
tl_i.a_address[21:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T66,*T67,*T76 Yes T66,T67,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T67,T76,T77 Yes T67,T76,T77 INPUT
tl_i.a_valid Yes Yes T4,T1,T105 Yes T4,T1,T105 INPUT
tl_o.a_ready Yes Yes T4,T1,T105 Yes T4,T1,T105 OUTPUT
tl_o.d_error Yes Yes T73,T75,T78 Yes T73,T75,T78 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T1,T105 Yes T4,T1,T105 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T1,T105 Yes T4,T1,T105 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T1,T105 Yes T4,T1,T105 OUTPUT
tl_o.d_sink Yes Yes T73,T78,T125 Yes T73,T74,T78 OUTPUT
tl_o.d_source[5:0] Yes Yes *T9,*T73,*T78 Yes T9,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T73,T74,T75 Yes T73,T74,T75 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T1,*T105 Yes T4,T1,T105 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T1,T105 Yes T4,T1,T105 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T4,T105,T270 Yes T4,T105,T270 INPUT
alert_rx_i[0].ping_n Yes Yes T4,T79,T80 Yes T79,T80,T81 INPUT
alert_rx_i[0].ping_p Yes Yes T79,T80,T81 Yes T4,T79,T80 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T4,T105,T270 Yes T4,T105,T270 OUTPUT
pwr_ast_i.main_pok Yes Yes T6,T1,T105 Yes T4,T5,T6 INPUT
pwr_ast_i.usb_clk_val Yes Yes T4,T6,T1 Yes T4,T5,T6 INPUT
pwr_ast_i.io_clk_val Yes Yes T4,T6,T1 Yes T4,T5,T6 INPUT
pwr_ast_i.core_clk_val Yes Yes T4,T6,T1 Yes T4,T5,T6 INPUT
pwr_ast_i.slow_clk_val Yes Yes T115,T116,T117 Yes T4,T5,T6 INPUT
pwr_ast_o.usb_clk_en Yes Yes T4,T6,T1 Yes T4,T5,T6 OUTPUT
pwr_ast_o.io_clk_en Yes Yes T4,T6,T1 Yes T4,T5,T6 OUTPUT
pwr_ast_o.core_clk_en Yes Yes T4,T6,T1 Yes T4,T5,T6 OUTPUT
pwr_ast_o.slow_clk_en No No No OUTPUT
pwr_ast_o.pwr_clamp Yes Yes T4,T5,T6 Yes T6,T1,T18 OUTPUT
pwr_ast_o.pwr_clamp_env Yes Yes T4,T5,T6 Yes T6,T1,T18 OUTPUT
pwr_ast_o.main_pd_n Yes Yes T1,T119,T120 Yes T1,T119,T120 OUTPUT
pwr_rst_i.rst_sys_src_n[1:0] Yes Yes T5,T6,T42 Yes T4,T5,T6 INPUT
pwr_rst_i.rst_lc_src_n[1:0] Yes Yes T5,T6,T42 Yes T4,T5,T6 INPUT
pwr_rst_o.reset_cause[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
pwr_rst_o.rstreqs[4:0] Yes Yes T451,T452,T453 Yes T451,T452,T453 OUTPUT
pwr_rst_o.rst_sys_req[1:0] Yes Yes T4,T5,T6 Yes T5,T6,T42 OUTPUT
pwr_rst_o.rst_lc_req[1:0] Yes Yes T4,T5,T6 Yes T5,T6,T42 OUTPUT
pwr_clk_o.usb_ip_clk_en Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
pwr_clk_o.io_ip_clk_en Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
pwr_clk_o.main_ip_clk_en Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
pwr_clk_i.usb_status Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
pwr_clk_i.io_status Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
pwr_clk_i.main_status Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
pwr_otp_i.otp_idle Yes Yes T5,T6,T42 Yes T4,T5,T6 INPUT
pwr_otp_i.otp_done Yes Yes T5,T6,T42 Yes T4,T5,T6 INPUT
pwr_otp_o.otp_init Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
pwr_lc_i.lc_idle Yes Yes T5,T6,T42 Yes T4,T5,T6 INPUT
pwr_lc_i.lc_done Yes Yes T5,T6,T42 Yes T4,T5,T6 INPUT
pwr_lc_o.lc_init Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
pwr_flash_i.flash_idle Yes Yes T6,T42,T108 Yes T6,T42,T108 INPUT
pwr_cpu_i.core_sleeping Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
fetch_en_o[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
lc_hw_debug_en_i[3:0] Yes Yes T5,T6,T42 Yes T4,T5,T6 INPUT
lc_dft_en_i[3:0] Yes Yes T5,T6,T42 Yes T4,T5,T6 INPUT
wakeups_i[5:0] Yes Yes T1,T451,T452 Yes T1,T451,T452 INPUT
rstreqs_i[1:0] Yes Yes T451,T452,T453 Yes T451,T452,T453 INPUT
ndmreset_req_i Yes Yes T66,T7,T8 Yes T66,T7,T8 INPUT
strap_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
low_power_o Yes Yes T4,T5,T6 Yes T4,T6,T1 OUTPUT
rom_ctrl_i.good[3:0] Yes Yes T4,T5,T6 Yes T5,T6,T42 INPUT
rom_ctrl_i.done[3:0] Yes Yes T4,T5,T6 Yes T5,T6,T42 INPUT
sw_rst_req_i[3:0] Yes Yes T6,T42,T182 Yes T6,T42,T182 INPUT
esc_rst_tx_i.esc_n Yes Yes T5,T61,T62 Yes T5,T61,T62 INPUT
esc_rst_tx_i.esc_p Yes Yes T5,T61,T62 Yes T5,T61,T62 INPUT
esc_rst_rx_o.resp_n Yes Yes T5,T61,T62 Yes T5,T61,T62 OUTPUT
esc_rst_rx_o.resp_p Yes Yes T5,T61,T62 Yes T5,T61,T62 OUTPUT
intr_wakeup_o Yes Yes T4,T1,T347 Yes T4,T1,T347 OUTPUT

*Tests covering at least one bit in the range
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