Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T176,T177,T9
0	1	Covered	T176,T177,T9
1	0	Covered	T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T9
1	Covered	T176,T177,T9

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T9
1	Covered	T176,T177,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T176,T177,T9
1	1	Covered	T176,T177,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T176,T177,T9
1	0	Covered	T176,T177,T9
1	1	Covered	T176,T177,T9

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T176,T177,T9

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T9
0	Covered	T176,T177,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T9
0	Covered	T176,T177,T9

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	956820906	939410322	0	0
CheckNGreaterZero_A	1994	1994	0	0
GntImpliesReady_A	956820906	8459	0	0
GntImpliesValid_A	956820906	8459	0	0
GrantKnown_A	956820906	939410322	0	0
IdxKnown_A	956820906	939410322	0	0
IndexIsCorrect_A	956820906	8459	0	0
NoReadyValidNoGrant_A	956820906	0	0	0
Priority_A	956820906	8459	0	0
ReadyAndValidImplyGrant_A	956820906	8459	0	0
ReqAndReadyImplyGrant_A	956820906	8459	0	0
ReqImpliesValid_A	956820906	8459	0	0
ValidKnown_A	956820906	939410322	0	0
gen_data_port_assertion.DataFlow_A	956820906	8459	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	939410322	0	0
T1	1238942	1238342	0	0
T4	293576	293460	0	0
T5	513054	512828	0	0
T6	824528	824468	0	0
T17	420962	420846	0	0
T42	999868	999628	0	0
T61	500422	500218	0	0
T70	314304	314294	0	0
T82	481904	481802	0	0
T83	177678	177576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1994	1994	0	0
T1	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T42	2	2	0	0
T61	2	2	0	0
T70	2	2	0	0
T82	2	2	0	0
T83	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	8459	0	0
T23	489108	0	0	0
T52	226138	0	0	0
T176	185716	2820	0	0
T177	0	2820	0	0
T229	1002526	0	0	0
T316	0	2819	0	0
T318	436814	0	0	0
T319	214232	0	0	0
T320	1277522	0	0	0
T321	327834	0	0	0
T322	448838	0	0	0
T323	84402	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	8459	0	0
T23	489108	0	0	0
T52	226138	0	0	0
T176	185716	2820	0	0
T177	0	2820	0	0
T229	1002526	0	0	0
T316	0	2819	0	0
T318	436814	0	0	0
T319	214232	0	0	0
T320	1277522	0	0	0
T321	327834	0	0	0
T322	448838	0	0	0
T323	84402	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	939410322	0	0
T1	1238942	1238342	0	0
T4	293576	293460	0	0
T5	513054	512828	0	0
T6	824528	824468	0	0
T17	420962	420846	0	0
T42	999868	999628	0	0
T61	500422	500218	0	0
T70	314304	314294	0	0
T82	481904	481802	0	0
T83	177678	177576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	939410322	0	0
T1	1238942	1238342	0	0
T4	293576	293460	0	0
T5	513054	512828	0	0
T6	824528	824468	0	0
T17	420962	420846	0	0
T42	999868	999628	0	0
T61	500422	500218	0	0
T70	314304	314294	0	0
T82	481904	481802	0	0
T83	177678	177576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	8459	0	0
T23	489108	0	0	0
T52	226138	0	0	0
T176	185716	2820	0	0
T177	0	2820	0	0
T229	1002526	0	0	0
T316	0	2819	0	0
T318	436814	0	0	0
T319	214232	0	0	0
T320	1277522	0	0	0
T321	327834	0	0	0
T322	448838	0	0	0
T323	84402	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	8459	0	0
T23	489108	0	0	0
T52	226138	0	0	0
T176	185716	2820	0	0
T177	0	2820	0	0
T229	1002526	0	0	0
T316	0	2819	0	0
T318	436814	0	0	0
T319	214232	0	0	0
T320	1277522	0	0	0
T321	327834	0	0	0
T322	448838	0	0	0
T323	84402	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	8459	0	0
T23	489108	0	0	0
T52	226138	0	0	0
T176	185716	2820	0	0
T177	0	2820	0	0
T229	1002526	0	0	0
T316	0	2819	0	0
T318	436814	0	0	0
T319	214232	0	0	0
T320	1277522	0	0	0
T321	327834	0	0	0
T322	448838	0	0	0
T323	84402	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	8459	0	0
T23	489108	0	0	0
T52	226138	0	0	0
T176	185716	2820	0	0
T177	0	2820	0	0
T229	1002526	0	0	0
T316	0	2819	0	0
T318	436814	0	0	0
T319	214232	0	0	0
T320	1277522	0	0	0
T321	327834	0	0	0
T322	448838	0	0	0
T323	84402	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	8459	0	0
T23	489108	0	0	0
T52	226138	0	0	0
T176	185716	2820	0	0
T177	0	2820	0	0
T229	1002526	0	0	0
T316	0	2819	0	0
T318	436814	0	0	0
T319	214232	0	0	0
T320	1277522	0	0	0
T321	327834	0	0	0
T322	448838	0	0	0
T323	84402	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	939410322	0	0
T1	1238942	1238342	0	0
T4	293576	293460	0	0
T5	513054	512828	0	0
T6	824528	824468	0	0
T17	420962	420846	0	0
T42	999868	999628	0	0
T61	500422	500218	0	0
T70	314304	314294	0	0
T82	481904	481802	0	0
T83	177678	177576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956820906	8459	0	0
T23	489108	0	0	0
T52	226138	0	0	0
T176	185716	2820	0	0
T177	0	2820	0	0
T229	1002526	0	0	0
T316	0	2819	0	0
T318	436814	0	0	0
T319	214232	0	0	0
T320	1277522	0	0	0
T321	327834	0	0	0
T322	448838	0	0	0
T323	84402	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T176,T177,T9
0	1	Covered	T176,T177,T316
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T316
1	Covered	T176,T177,T9

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T316
1	Covered	T176,T177,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T176,T177,T316
1	1	Covered	T176,T177,T316

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T176,T177,T9
1	0	Covered	T176,T177,T316
1	1	Covered	T176,T177,T316

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T176,T177,T316

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T9
0	Covered	T176,T177,T316

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T9
0	Covered	T176,T177,T316

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	478410453	469705161	0	0
CheckNGreaterZero_A	997	997	0	0
GntImpliesReady_A	478410453	5274	0	0
GntImpliesValid_A	478410453	5274	0	0
GrantKnown_A	478410453	469705161	0	0
IdxKnown_A	478410453	469705161	0	0
IndexIsCorrect_A	478410453	5274	0	0
NoReadyValidNoGrant_A	478410453	0	0	0
Priority_A	478410453	5274	0	0
ReadyAndValidImplyGrant_A	478410453	5274	0	0
ReqAndReadyImplyGrant_A	478410453	5274	0	0
ReqImpliesValid_A	478410453	5274	0	0
ValidKnown_A	478410453	469705161	0	0
gen_data_port_assertion.DataFlow_A	478410453	5274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	469705161	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	997	997	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	5274	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1758	0	0
T177	0	1758	0	0
T229	501263	0	0	0
T316	0	1758	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	5274	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1758	0	0
T177	0	1758	0	0
T229	501263	0	0	0
T316	0	1758	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	469705161	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	469705161	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	5274	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1758	0	0
T177	0	1758	0	0
T229	501263	0	0	0
T316	0	1758	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	5274	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1758	0	0
T177	0	1758	0	0
T229	501263	0	0	0
T316	0	1758	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	5274	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1758	0	0
T177	0	1758	0	0
T229	501263	0	0	0
T316	0	1758	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	5274	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1758	0	0
T177	0	1758	0	0
T229	501263	0	0	0
T316	0	1758	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	5274	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1758	0	0
T177	0	1758	0	0
T229	501263	0	0	0
T316	0	1758	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	469705161	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	5274	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1758	0	0
T177	0	1758	0	0
T229	501263	0	0	0
T316	0	1758	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T176,T177,T9
0	1	Covered	T176,T177,T9
1	0	Covered	T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T9
1	Covered	T176,T177,T9

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T177,T9
1	Covered	T176,T177,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T176,T177,T9
1	1	Covered	T176,T177,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T176,T177,T9
1	0	Covered	T176,T177,T9
1	1	Covered	T176,T177,T9

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T176,T177,T9

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T9
0	Covered	T176,T177,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T177,T9
0	Covered	T176,T177,T9

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	478410453	469705161	0	0
CheckNGreaterZero_A	997	997	0	0
GntImpliesReady_A	478410453	3185	0	0
GntImpliesValid_A	478410453	3185	0	0
GrantKnown_A	478410453	469705161	0	0
IdxKnown_A	478410453	469705161	0	0
IndexIsCorrect_A	478410453	3185	0	0
NoReadyValidNoGrant_A	478410453	0	0	0
Priority_A	478410453	3185	0	0
ReadyAndValidImplyGrant_A	478410453	3185	0	0
ReqAndReadyImplyGrant_A	478410453	3185	0	0
ReqImpliesValid_A	478410453	3185	0	0
ValidKnown_A	478410453	469705161	0	0
gen_data_port_assertion.DataFlow_A	478410453	3185	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	469705161	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	997	997	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T61	1	1	0	0
T70	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	3185	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1062	0	0
T177	0	1062	0	0
T229	501263	0	0	0
T316	0	1061	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	3185	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1062	0	0
T177	0	1062	0	0
T229	501263	0	0	0
T316	0	1061	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	469705161	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	469705161	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	3185	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1062	0	0
T177	0	1062	0	0
T229	501263	0	0	0
T316	0	1061	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	3185	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1062	0	0
T177	0	1062	0	0
T229	501263	0	0	0
T316	0	1061	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	3185	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1062	0	0
T177	0	1062	0	0
T229	501263	0	0	0
T316	0	1061	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	3185	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1062	0	0
T177	0	1062	0	0
T229	501263	0	0	0
T316	0	1061	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	3185	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1062	0	0
T177	0	1062	0	0
T229	501263	0	0	0
T316	0	1061	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	469705161	0	0
T1	619471	619171	0	0
T4	146788	146730	0	0
T5	256527	256414	0	0
T6	412264	412234	0	0
T17	210481	210423	0	0
T42	499934	499814	0	0
T61	250211	250109	0	0
T70	157152	157147	0	0
T82	240952	240901	0	0
T83	88839	88788	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478410453	3185	0	0
T23	244554	0	0	0
T52	113069	0	0	0
T176	92858	1062	0	0
T177	0	1062	0	0
T229	501263	0	0	0
T316	0	1061	0	0
T318	218407	0	0	0
T319	107116	0	0	0
T320	638761	0	0	0
T321	163917	0	0	0
T322	224419	0	0	0
T323	42201	0	0	0