Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1391242	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33067865

1

T4

140240

T5

110947

T6

91356

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23644267	1			T4	119157		T5	98180		T6	84155
values[0x0]	9422721	1			T4	21083		T5	12767		T6	7201
values[0x1]	1392119	1			T4	20		T5	4		T6	647

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10012	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34449095

1

T4

140260

T5

110951

T6

92003

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17214155	1			T4	70130		T5	55476		T6	46002
valid_sources[0x01]	17213196	1			T4	70130		T5	55475		T6	46001
valid_sources[0x02]	371	1			T76	1		T56	49		T215	51
valid_sources[0x03]	303	1			T56	55		T215	58		T217	36
valid_sources[0x04]	3282	1			T26	1		T55	2989		T56	26
valid_sources[0x05]	348	1			T76	1		T56	88		T215	45
valid_sources[0x06]	344	1			T22	1		T76	2		T26	1
valid_sources[0x07]	298	1			T56	76		T215	46		T217	49
valid_sources[0x08]	413	1			T76	1		T56	60		T215	47
valid_sources[0x09]	320	1			T76	2		T56	61		T215	62
valid_sources[0x0a]	300	1			T22	1		T26	3		T56	75
valid_sources[0x0b]	334	1			T22	2		T56	87		T57	16
valid_sources[0x0c]	427	1			T56	87		T215	57		T217	78
valid_sources[0x0d]	414	1			T22	3		T56	58		T215	55
valid_sources[0x0e]	308	1			T22	3		T76	1		T56	48
valid_sources[0x0f]	309	1			T26	1		T56	42		T215	64
valid_sources[0x10]	413	1			T22	2		T56	88		T215	61
valid_sources[0x11]	444	1			T76	1		T26	1		T55	16
valid_sources[0x12]	352	1			T76	3		T26	4		T56	51
valid_sources[0x13]	483	1			T76	1		T97	4		T55	126
valid_sources[0x14]	381	1			T26	1		T97	6		T56	60
valid_sources[0x15]	341	1			T22	2		T76	1		T56	64
valid_sources[0x16]	3016	1			T22	1		T26	1		T56	78
valid_sources[0x17]	324	1			T26	1		T56	63		T57	32
valid_sources[0x18]	283	1			T56	69		T215	38		T217	22
valid_sources[0x19]	458	1			T76	2		T55	16		T56	105
valid_sources[0x1a]	306	1			T76	1		T26	5		T56	16
valid_sources[0x1b]	273	1			T26	3		T56	32		T215	61
valid_sources[0x1c]	338	1			T76	1		T231	39		T26	1
valid_sources[0x1d]	342	1			T22	1		T56	60		T215	56
valid_sources[0x1e]	304	1			T22	1		T76	2		T97	6
valid_sources[0x1f]	417	1			T22	1		T26	3		T56	70
valid_sources[0x20]	375	1			T76	2		T56	86		T215	64

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23644267

1

T4

119157

T5

98180

T6

84155

values[0x0]

all_enables

biggest_size

9417618

1

T4

21083

T5

12767

T6

7201

values[0x1]

all_enables

biggest_size

5980

1

T22

20

T24

18

T76

18