Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491570711	55091653	0	0
DepthKnown_A	491570711	491464896	0	0
RvalidKnown_A	491570711	491464896	0	0
WreadyKnown_A	491570711	491464896	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	55091653	0	0
T4	142498	151967	0	0
T5	122533	135708	0	0
T6	737721	103785	0	0
T17	214832	25702	0	0
T30	283999	29732	0	0
T31	161782	24399	0	0
T58	112394	14107	0	0
T93	472771	40105	0	0
T95	93145	10360	0	0
T96	95721	11219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491570711	42882736	0	0
DepthKnown_A	491570711	491464896	0	0
RvalidKnown_A	491570711	491464896	0	0
WreadyKnown_A	491570711	491464896	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	42882736	0	0
T4	142498	133399	0	0
T5	122533	118099	0	0
T6	737721	96989	0	0
T17	214832	19913	0	0
T30	283999	25315	0	0
T31	161782	17842	0	0
T58	112394	11044	0	0
T93	472771	36166	0	0
T95	93145	8072	0	0
T96	95721	8953	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491570711	41045730	0	0
DepthKnown_A	491570711	491464896	0	0
RvalidKnown_A	491570711	491464896	0	0
WreadyKnown_A	491570711	491464896	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	41045730	0	0
T4	142498	209178	0	0
T5	122533	173552	0	0
T6	737721	92403	0	0
T17	214832	15501	0	0
T30	283999	25279	0	0
T31	161782	9735	0	0
T58	112394	10866	0	0
T93	472771	44521	0	0
T95	93145	8718	0	0
T96	95721	7058	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491570711	34566353	0	0
DepthKnown_A	491570711	491464896	0	0
RvalidKnown_A	491570711	491464896	0	0
WreadyKnown_A	491570711	491464896	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	34566353	0	0
T4	142498	140260	0	0
T5	122533	110951	0	0
T6	737721	92003	0	0
T17	214832	15121	0	0
T30	283999	24984	0	0
T31	161782	9458	0	0
T58	112394	10706	0	0
T93	472771	44260	0	0
T95	93145	8358	0	0
T96	95721	6871	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491570711	65477	0	0
DepthKnown_A	491570711	491464896	0	0
RvalidKnown_A	491570711	491464896	0	0
WreadyKnown_A	491570711	491464896	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	65477	0	0
T4	142498	41	0	0
T5	122533	34	0	0
T6	737721	39	0	0
T17	214832	104	0	0
T30	283999	23	0	0
T31	161782	26	0	0
T58	112394	68	0	0
T93	472771	91	0	0
T95	93145	14	0	0
T96	95721	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491570711	65477	0	0
DepthKnown_A	491570711	491464896	0	0
RvalidKnown_A	491570711	491464896	0	0
WreadyKnown_A	491570711	491464896	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	65477	0	0
T4	142498	41	0	0
T5	122533	34	0	0
T6	737721	39	0	0
T17	214832	104	0	0
T30	283999	23	0	0
T31	161782	26	0	0
T58	112394	68	0	0
T93	472771	91	0	0
T95	93145	14	0	0
T96	95721	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491570711	51739	0	0
DepthKnown_A	491570711	491464896	0	0
RvalidKnown_A	491570711	491464896	0	0
WreadyKnown_A	491570711	491464896	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	51739	0	0
T4	142498	12	0	0
T5	122533	5	0	0
T6	737721	37	0	0
T17	214832	98	0	0
T30	283999	20	0	0
T31	161782	23	0	0
T58	112394	67	0	0
T93	472771	90	0	0
T95	93145	13	0	0
T96	95721	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491570711	51739	0	0
DepthKnown_A	491570711	491464896	0	0
RvalidKnown_A	491570711	491464896	0	0
WreadyKnown_A	491570711	491464896	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	51739	0	0
T4	142498	12	0	0
T5	122533	5	0	0
T6	737721	37	0	0
T17	214832	98	0	0
T30	283999	20	0	0
T31	161782	23	0	0
T58	112394	67	0	0
T93	472771	90	0	0
T95	93145	13	0	0
T96	95721	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491570711	13738	0	0
DepthKnown_A	491570711	491464896	0	0
RvalidKnown_A	491570711	491464896	0	0
WreadyKnown_A	491570711	491464896	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	13738	0	0
T4	142498	29	0	0
T5	122533	29	0	0
T6	737721	2	0	0
T17	214832	6	0	0
T30	283999	3	0	0
T31	161782	3	0	0
T58	112394	1	0	0
T93	472771	1	0	0
T95	93145	1	0	0
T96	95721	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491570711	13738	0	0
DepthKnown_A	491570711	491464896	0	0
RvalidKnown_A	491570711	491464896	0	0
WreadyKnown_A	491570711	491464896	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	13738	0	0
T4	142498	29	0	0
T5	122533	29	0	0
T6	737721	2	0	0
T17	214832	6	0	0
T30	283999	3	0	0
T31	161782	3	0	0
T58	112394	1	0	0
T93	472771	1	0	0
T95	93145	1	0	0
T96	95721	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	491464896	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0