Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.31 94.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main 94.17 94.17
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 94.90 94.90


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.17 94.17


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.17 94.17


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.12 88.53 87.83 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.90 94.90


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.90 94.90


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.12 88.53 87.83 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 64 46 71.88
Total Bits 1160 1094 94.31
Total Bits 0->1 580 547 94.31
Total Bits 1->0 580 547 94.31

Ports 64 46 71.88
Port Bits 1160 1094 94.31
Port Bits 0->1 580 547 94.31
Port Bits 1->0 580 547 94.31

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
ram_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_error Yes Yes T4,T5,T6 Yes T6,T17,T18 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[5:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T4,*T5,*T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T22,*T23,*T20 Yes T22,T23,T20 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T22,*T24,*T76 Yes T22,T24,T76 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_valid Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_o.a_ready Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T17,T113,T114 Yes T17,T113,T114 OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T17,T33,T113 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T17,*T33,T113 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T17,T33,T113 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T26,*T17,*T33 Yes T26,T4,T5 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T17,T33,T113 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T17,*T113,*T114 Yes T17,T113,T114 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_rx_i[0].ping_n Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_rx_i[0].ping_p Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T27,T29,T128 Yes T27,T29,T128 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T19,T86,T77 Yes T19,T86,T77 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T6,T17,T19 Yes T4,T5,T6 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T4,T5,T6 Yes T6,T17,T18 INPUT
sram_otp_key_o.req Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i.ack Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 60 41 68.33
Total Bits 1132 1066 94.17
Total Bits 0->1 566 533 94.17
Total Bits 1->0 566 533 94.17

Ports 60 41 68.33
Port Bits 1132 1066 94.17
Port Bits 0->1 566 533 94.17
Port Bits 1->0 566 533 94.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
ram_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_source[5] No No No INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[0] No No No INPUT
ram_tl_i.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_error Yes Yes T4,T5,T6 Yes T6,T17,T18 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_user.cmd_intg[1] No No No INPUT
regs_tl_i.a_user.cmd_intg[6:2] Yes Yes T17,T113,T114 Yes T17,T113,T114 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes *T4,*T5,*T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_address[5] No No No INPUT
regs_tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T4,*T5,*T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T4,*T5,*T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[1:0] Yes Yes *T26,*T4,*T5 Yes T26,T4,T5 INPUT
regs_tl_i.a_source[5:2] No No No INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[0] No No No INPUT
regs_tl_i.a_size[1] Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[1:0] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T17,T113,T114 Yes T17,T113,T114 INPUT
regs_tl_i.a_valid Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_o.a_ready Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T115,T116,T26 Yes T115,T116,T26 OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T17,T33,T113 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T17,*T33,T113 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T17,T33,T113 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T26,*T17,*T33 Yes T26,T4,T5 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T17,T33,T113 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T17,*T113,*T114 Yes T17,T113,T114 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_rx_i[0].ping_n Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_rx_i[0].ping_p Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T27,T29,T128 Yes T27,T29,T128 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T19,T86,T77 Yes T19,T86,T77 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T6,T17,T19 Yes T4,T5,T6 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T4,T5,T6 Yes T6,T17,T18 INPUT
sram_otp_key_o.req Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i.ack Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 58 43 74.14
Total Bits 1098 1042 94.90
Total Bits 0->1 549 521 94.90
Total Bits 1->0 549 521 94.90

Ports 58 43 74.14
Port Bits 1098 1042 94.90
Port Bits 0->1 549 521 94.90
Port Bits 1->0 549 521 94.90

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
ram_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[2:1] No No No INPUT
ram_tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[11:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T22,*T23,*T20 Yes T22,T23,T20 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T22,*T24,*T76 Yes T22,T24,T76 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_error Yes Yes T4,T5,T6 Yes T6,T17,T18 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[1:0] Yes Yes *T22,*T24,*T231 Yes T22,T24,T231 OUTPUT
ram_tl_o.d_source[5:2] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[5:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[19:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T22,*T23,*T20 Yes T22,T23,T20 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T22,*T24,*T76 Yes T22,T24,T76 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_valid Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
regs_tl_o.a_ready Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T17,T113,T114 Yes T17,T113,T114 OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T17,T33,T113 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes *T33,*T68,*T69 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T17,T33,T113 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T26,*T17,*T113 Yes T26,T17,T113 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T33,T68,T69 Yes T4,T5,T17 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T17,*T113,*T114 Yes T17,T113,T114 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_rx_i[0].ping_n Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_rx_i[0].ping_p Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T27,T29,T128 Yes T27,T29,T128 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T19,T86,T77 Yes T19,T86,T77 INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req Yes Yes T17,T113,T114 Yes T17,T113,T114 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sram_otp_key_i.ack Yes Yes T17,T113,T114 Yes T17,T113,T114 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%