Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.65 84.65

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_usbdev 84.65 84.65



Module Instance : tb.dut.top_earlgrey.u_usbdev

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.65 84.65


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.65 84.65


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.12 88.53 87.83 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : usbdev
TotalCoveredPercent
Totals 75 61 81.33
Total Bits 404 342 84.65
Total Bits 0->1 202 171 84.65
Total Bits 1->0 202 171 84.65

Ports 75 61 81.33
Port Bits 404 342 84.65
Port Bits 0->1 202 171 84.65
Port Bits 1->0 202 171 84.65

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_aon_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T87,*T88 Yes T1,T87,T88 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[11:2] Yes Yes *T87,*T88,*T92 Yes T87,T88,T92 INPUT
tl_i.a_address[16:12] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T1,*T87,*T88 Yes T1,T87,T88 INPUT
tl_i.a_address[19:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T87,*T88 Yes T1,T87,T88 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T26,*T87,*T88 Yes T26,T87,T88 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T87,T88,T92 Yes T87,T88,T92 INPUT
tl_i.a_valid Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_o.a_ready Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T87,T88,T92 Yes T87,T88,T92 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T87,T88,T92 Yes T87,T88,T92 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T26,*T87,*T88 Yes T26,T87,T88 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T87,*T88 Yes T1,T87,T88 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_rx_i[0].ping_n Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_rx_i[0].ping_p Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T27,T29,T128 Yes T27,T29,T128 OUTPUT
cio_usb_dp_i Yes Yes T125,T130,T126 Yes T125,T126,T48 INPUT
cio_usb_dn_i Yes Yes T125,T126,T48 Yes T125,T126,T48 INPUT
usb_rx_d_i Yes Yes T125,T126,T48 Yes T125,T126,T48 INPUT
cio_usb_dp_o Yes Yes T1,T44,T2 Yes T1,T44,T7 OUTPUT
cio_usb_dp_en_o Yes Yes T48,T49,T50 Yes T48,T49,T50 OUTPUT
cio_usb_dn_o Yes Yes T125,T126,T48 Yes T125,T130,T126 OUTPUT
cio_usb_dn_en_o Yes Yes T48,T49,T50 Yes T48,T49,T50 OUTPUT
usb_tx_se0_o Yes Yes T48,T49,T50 Yes T48,T49,T50 OUTPUT
usb_tx_d_o Yes Yes T1,T44,T2 Yes T1,T44,T7 OUTPUT
cio_sense_i Yes Yes T50,T55,T56 Yes T125,T130,T126 INPUT
usb_dp_pullup_o Yes Yes T1,T44,T7 Yes T1,T44,T2 OUTPUT
usb_dn_pullup_o Yes Yes T125,T126,T50 Yes T125,T126,T50 OUTPUT
usb_rx_enable_o Yes Yes T26,T50 Yes T125,T126,T48 OUTPUT
usb_tx_use_d_se0_o Yes Yes T26 Yes T26 OUTPUT
usb_aon_suspend_req_o Yes Yes T1,T44,T2 Yes T1,T44,T2 OUTPUT
usb_aon_wake_ack_o Yes Yes T1,T44,T2 Yes T1,T44,T2 OUTPUT
usb_aon_bus_reset_i Yes Yes T125 Yes T125 INPUT
usb_aon_sense_lost_i Yes Yes T1,T2,T7 Yes T1,T44,T2 INPUT
usb_aon_bus_not_idle_i Yes Yes T1,T2,T7 Yes T1,T2,T7 INPUT
usb_aon_wake_detect_active_i Yes Yes T1,T2,T7 Yes T1,T44,T2 INPUT
usb_ref_val_o Yes Yes T48,T49,T50 Yes T48,T49,T50 OUTPUT
usb_ref_pulse_o Yes Yes T48,T49,T50 Yes T48,T49,T50 OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
intr_pkt_received_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_pkt_sent_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_powered_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_disconnected_o Yes Yes T92,T201,T26 Yes T92,T201,T26 OUTPUT
intr_host_lost_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_link_reset_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_link_suspend_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_link_resume_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_av_out_empty_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_rx_full_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_av_overflow_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_link_in_err_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_link_out_err_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_rx_crc_err_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_rx_pid_err_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_rx_bitstuff_err_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_frame_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT
intr_av_setup_empty_o Yes Yes T92,T201,T202 Yes T92,T201,T202 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%