Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	90.13			90.13
tb.dut.top_earlgrey.u_uart1	90.20			90.20
tb.dut.top_earlgrey.u_uart2	90.20			90.20
tb.dut.top_earlgrey.u_uart3	90.26			90.26

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.12	88.53		87.83			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.12	88.53		87.83			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.12	88.53		87.83			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.12	88.53		87.83			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	278	90.26
Total Bits 0->1	154	139	90.26
Total Bits 1->0	154	139	90.26

Ports	40	32	80.00
Port Bits	308	278	90.26
Port Bits 0->1	154	139	90.26
Port Bits 1->0	154	139	90.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T23,*T20	Yes	T22,T23,T20	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T22,*T24,*T76	Yes	T22,T24,T76	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T33,T321,T322	Yes	T33,T321,T322	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T33,T321,T322	Yes	T4,T5,T33	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T33,T68,T69	Yes	T4,T5,T33	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T33,T321,T322	Yes	T4,T5,T33	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T25,*T337,*T26	Yes	T25,T337,T26	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T33,T68,T69	Yes	T4,T5,T33	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T33,*T321,*T322	Yes	T33,T321,T322	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T31,T27,T29	Yes	T31,T27,T29	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T27,T29,T342	Yes	T27,T29,T128	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T342	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T31,T27,T29	Yes	T31,T27,T29	OUTPUT
cio_rx_i	Yes	Yes	T6,T17,T18	Yes	T6,T30,T58	INPUT
cio_tx_o	Yes	Yes	T33,T321,T322	Yes	T33,T321,T322	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T321,T322,T92	Yes	T321,T322,T92	OUTPUT
intr_tx_empty_o	Yes	Yes	T321,T322,T92	Yes	T321,T322,T92	OUTPUT
intr_rx_watermark_o	Yes	Yes	T321,T322,T92	Yes	T321,T322,T92	OUTPUT
intr_tx_done_o	Yes	Yes	T321,T322,T92	Yes	T321,T322,T92	OUTPUT
intr_rx_overflow_o	Yes	Yes	T321,T322,T92	Yes	T321,T322,T92	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_break_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_timeout_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	40	32	80.00
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T23,*T20	Yes	T22,T23,T20	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T22,*T24,*T76	Yes	T22,T24,T76	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T33,T321,T322	Yes	T33,T321,T322	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T33,T321,T322	Yes	T4,T5,T33	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T33,T68,T69	Yes	T4,T5,T33	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T33,T321,T322	Yes	T4,T5,T33	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T25,*T337,*T26	Yes	T25,T337,T26	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T33,T68,T69	Yes	T4,T5,T33	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T33,*T321,*T322	Yes	T33,T321,T322	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T27,T29,T342	Yes	T27,T29,T342	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T27,T29,T342	Yes	T29,T128,T263	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T29,T128,T263	Yes	T27,T29,T342	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T27,T29,T342	Yes	T27,T29,T342	OUTPUT
cio_rx_i	Yes	Yes	T6,T17,T18	Yes	T6,T30,T58	INPUT
cio_tx_o	Yes	Yes	T33,T321,T322	Yes	T33,T321,T322	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T321,T322,T92	Yes	T321,T322,T92	OUTPUT
intr_tx_empty_o	Yes	Yes	T321,T322,T92	Yes	T321,T322,T92	OUTPUT
intr_rx_watermark_o	Yes	Yes	T321,T322,T92	Yes	T321,T322,T92	OUTPUT
intr_tx_done_o	Yes	Yes	T321,T322,T92	Yes	T321,T322,T92	OUTPUT
intr_rx_overflow_o	Yes	Yes	T321,T322,T92	Yes	T321,T322,T92	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_break_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_timeout_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	40	32	80.00
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T23,*T20	Yes	T22,T23,T20	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T22,*T24,*T76	Yes	T22,T24,T76	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	INPUT
tl_o.a_ready	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T245,*T26,*T338	Yes	T92,T269,T316	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T26,*T92,*T269	Yes	T26,T92,T269	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T245,T26,T338	Yes	T92,T269,T316	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T92,*T269,*T316	Yes	T92,T269,T316	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T31,T27,T29	Yes	T31,T27,T29	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T31,T27,T29	Yes	T31,T27,T29	OUTPUT
cio_rx_i	Yes	Yes	T269,T316,T317	Yes	T269,T316,T317	INPUT
cio_tx_o	Yes	Yes	T269,T316,T317	Yes	T269,T316,T317	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	OUTPUT
intr_tx_empty_o	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	OUTPUT
intr_rx_watermark_o	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	OUTPUT
intr_tx_done_o	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	OUTPUT
intr_rx_overflow_o	Yes	Yes	T92,T269,T316	Yes	T92,T269,T316	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_break_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_timeout_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	40	32	80.00
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T23,*T20	Yes	T22,T23,T20	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T22,*T24,*T76	Yes	T22,T24,T76	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	INPUT
tl_o.a_ready	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T245,*T26,*T338	Yes	T92,T165,T166	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T26,*T92,*T165	Yes	T26,T92,T165	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T245,T26,T338	Yes	T92,T165,T166	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T92,*T165,*T166	Yes	T92,T165,T166	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	OUTPUT
cio_rx_i	Yes	Yes	T165,T166,T343	Yes	T165,T166,T343	INPUT
cio_tx_o	Yes	Yes	T165,T166,T343	Yes	T165,T166,T343	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	OUTPUT
intr_tx_empty_o	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	OUTPUT
intr_rx_watermark_o	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	OUTPUT
intr_tx_done_o	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	OUTPUT
intr_rx_overflow_o	Yes	Yes	T92,T165,T166	Yes	T92,T165,T166	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_break_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_timeout_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	278	90.26
Total Bits 0->1	154	139	90.26
Total Bits 1->0	154	139	90.26

Ports	40	32	80.00
Port Bits	308	278	90.26
Port Bits 0->1	154	139	90.26
Port Bits 1->0	154	139	90.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T23,*T20	Yes	T22,T23,T20	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T22,*T24,*T76	Yes	T22,T24,T76	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	INPUT
tl_o.a_ready	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T245,*T26,*T338	Yes	T32,T42,T43	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T26,*T32,*T42	Yes	T26,T32,T42	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T245,T26,T338	Yes	T32,T42,T43	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T32,*T42,*T43	Yes	T32,T42,T43	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	OUTPUT
cio_rx_i	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	INPUT
cio_tx_o	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
intr_tx_empty_o	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
intr_rx_watermark_o	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
intr_tx_done_o	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
intr_rx_overflow_o	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_break_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_timeout_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T92,T201,T202	Yes	T92,T201,T202	OUTPUT

*Tests covering at least one bit in the range