Module Definition
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Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Module : prim_sync_reqack
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T1
11CoveredT4,T5,T6

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT4,T5,T6

Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T4,T5,T6
EVEN 0 - Covered T4,T5,T1
ODD - 1 Covered T4,T5,T30
ODD - 0 Covered T4,T5,T6


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T4,T5,T6
EVEN 0 - Covered T4,T5,T6
ODD - 1 Covered T4,T5,T30
ODD - 0 Covered T4,T5,T6


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 735503644 4353 0 0
SyncReqAckHoldReq 984703496 4353 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 735503644 4353 0 0
T1 158161 3 0 0
T2 0 3 0 0
T3 0 1 0 0
T4 142498 15 0 0
T5 122533 15 0 0
T6 737721 2 0 0
T7 0 3 0 0
T10 0 1 0 0
T11 0 6 0 0
T12 0 1 0 0
T13 0 1 0 0
T17 214832 4 0 0
T28 38099 0 0 0
T30 283999 2 0 0
T31 161782 2 0 0
T33 277108 0 0 0
T58 112394 1 0 0
T71 11536 0 0 0
T86 54712 0 0 0
T93 472771 1 0 0
T95 93145 1 0 0
T96 95721 1 0 0
T99 97185 0 0 0
T141 0 3 0 0
T142 0 3 0 0
T143 41971 0 0 0
T144 29812 0 0 0
T145 37083 0 0 0
T146 42731 0 0 0
T194 21621 8 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 984703496 4353 0 0
T1 4070 3 0 0
T2 0 3 0 0
T3 0 1 0 0
T4 142498 15 0 0
T5 122533 15 0 0
T6 737721 2 0 0
T7 0 3 0 0
T10 0 1 0 0
T11 0 6 0 0
T12 0 1 0 0
T13 0 1 0 0
T17 214832 4 0 0
T28 513 0 0 0
T30 283999 2 0 0
T31 161782 2 0 0
T33 2583 0 0 0
T58 112394 1 0 0
T71 279 0 0 0
T86 827 0 0 0
T93 472771 1 0 0
T95 93145 1 0 0
T96 95721 1 0 0
T99 1138 0 0 0
T141 0 3 0 0
T142 0 3 0 0
T143 585 0 0 0
T144 484 0 0 0
T145 531 0 0 0
T146 686 0 0 0
T194 88508 8 0 0

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