Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.51 77.51

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 77.51 77.51


Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.51 77.51


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.51 77.51


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.12 88.53 87.83 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 290 52.73
Total Bits 6824 5289 77.51
Total Bits 0->1 3412 2645 77.52
Total Bits 1->0 3412 2644 77.49

Ports 550 290 52.73
Port Bits 6824 5289 77.51
Port Bits 0->1 3412 2645 77.52
Port Bits 1->0 3412 2644 77.49

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_fixed_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host0_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host1_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_main_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
rst_fixed_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
rst_usb_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
rst_spi_host0_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
rst_spi_host1_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.d_ready No No No INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_source[5:3] No No No INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T73,T74,T75 Yes T73,T74,T75 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0] Yes Yes *T73,*T74,*T75 Yes T73,T74,T75 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_sink No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[0] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T22,T24,T76 Yes T22,T24,T76 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T76,T26,T55 Yes T76,T26,T55 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T76,T26,T55 Yes T76,T26,T55 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_opcode[1] No No No INPUT
tl_rv_core_ibex__cored_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T77,T73,T74 Yes T77,T73,T74 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_sink No No No OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T6,T17,T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T22,T23,T20 Yes T22,T23,T20 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T6,T17,T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.instr_type[0] Yes Yes *T6,*T17,*T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1] No No No INPUT
tl_rv_dm__sba_i.a_user.instr_type[3] Yes Yes T6,T17,T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T22,T23,T20 Yes T22,T23,T20 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T6,T17,T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] No No No INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[0] No No No INPUT
tl_rv_dm__sba_i.a_size[1] Yes Yes T6,T17,T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[1:0] No No No INPUT
tl_rv_dm__sba_i.a_opcode[2] Yes Yes T6,T17,T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T22,T23,T20 Yes T22,T23,T20 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T6,T17,T18 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_o.d_error No No No OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T22,T23,T20 Yes T22,T23,T20 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0] Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2] No No No OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3] Yes Yes T22,T23,*T20 Yes T22,T23,T20 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T22,T20,T24 Yes T22,T20,T24 OUTPUT
tl_rv_dm__sba_o.d_sink No No No OUTPUT
tl_rv_dm__sba_o.d_source[5:0] No No No OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[0] No No No OUTPUT
tl_rv_dm__sba_o.d_size[1] Yes Yes T22,T23,T20 Yes T22,T23,T20 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T22,*T23,*T20 Yes T22,T23,T20 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T22,T23,T20 Yes T22,T23,T20 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T6,T17,T18 Yes T4,T5,T6 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[31:0] No No No OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] No No No OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[5:0] No No No OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[1:0] No No No OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0] No No No OUTPUT
tl_rv_dm__regs_o.a_valid No No No OUTPUT
tl_rv_dm__regs_i.a_ready No No No INPUT
tl_rv_dm__regs_i.d_error No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] No No No INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] No No No INPUT
tl_rv_dm__regs_i.d_data[31:0] No No No INPUT
tl_rv_dm__regs_i.d_sink No No No INPUT
tl_rv_dm__regs_i.d_source[5:0] No No No INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[1:0] No No No INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] No No No INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid No No No INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T6,T17,T18 Yes T4,T5,T6 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T20,T25,T21 Yes T20,T25,T21 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T20,T25,T21 Yes T20,T25,T21 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T20,T25,T21 Yes T20,T25,T21 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T20,T25,T21 Yes T20,T25,T21 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T20,T25,T21 Yes T20,T25,T21 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[4:0] Yes Yes *T20,*T25,*T21 Yes T20,T25,T21 OUTPUT
tl_rv_dm__mem_o.a_source[5] No No No OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[0] No No No OUTPUT
tl_rv_dm__mem_o.a_size[1] Yes Yes T20,T25,T21 Yes T20,T25,T21 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__mem_o.a_opcode[2] Yes Yes T20,T25,T21 Yes T20,T25,T21 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T20,T25,T21 Yes T20,T25,T21 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T4,T5,T6 Yes T6,T17,T19 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T20,T25,T21 Yes T20,T25,T21 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0] Yes Yes *T20,*T25,*T21 Yes T20,T25,T21 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4] Yes Yes *T20,*T21,*T26 Yes T20,T25,T21 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T6,T17,T19 INPUT
tl_rv_dm__mem_i.d_sink No No No INPUT
tl_rv_dm__mem_i.d_source[4:0] Yes Yes *T20,*T25,*T21 Yes T20,T25,T21 INPUT
tl_rv_dm__mem_i.d_source[5] No No No INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[0] No No No INPUT
tl_rv_dm__mem_i.d_size[1] Yes Yes T20,T21,T26 Yes T20,T25,T21 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T6,T17,T19 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T20,T25,T21 Yes T20,T25,T21 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T4,T5,T33 Yes T4,T5,T33 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_source[5] No No No OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_error No No No INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5] No No No INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_sink No No No INPUT
tl_rom_ctrl__rom_i.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_source[5] No No No INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[0] No No No INPUT
tl_rom_ctrl__rom_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] No No No INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T6,T17,T18 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[5:3] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[0] Yes Yes *T78,*T79,*T80 Yes T78,T79,T80 OUTPUT
tl_rom_ctrl__regs_o.a_data[31:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[1] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_size[1] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_rom_ctrl__regs_i.d_error No No No INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T82,T84,T85 Yes T82,T84,T85 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[0] No No Yes T78,T79,T80 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1] No Yes *T78,*T79,*T80 No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T82,T84,T85 Yes T82,T78,T84 INPUT
tl_rom_ctrl__regs_i.d_sink No No No INPUT
tl_rom_ctrl__regs_i.d_source[0] No No No INPUT
tl_rom_ctrl__regs_i.d_source[1] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 INPUT
tl_rom_ctrl__regs_i.d_source[5:2] No No No INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[0] No No No INPUT
tl_rom_ctrl__regs_i.d_size[1] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_peri_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.instr_type[2:1] No No No OUTPUT
tl_peri_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes *T22,*T23,*T20 Yes T22,T23,T20 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[0] Yes Yes *T22,*T24,*T76 Yes T22,T24,T76 OUTPUT
tl_peri_o.a_opcode[1] No No No OUTPUT
tl_peri_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_error Yes Yes T86,T77,T73 Yes T86,T77,T73 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_user.rsp_intg[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_user.rsp_intg[6] No No No INPUT
tl_peri_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_sink No No No INPUT
tl_peri_i.d_source[5:0] Yes Yes *T22,*T23,*T20 Yes T22,T23,T20 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_spi_host0_o.d_ready Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_o.a_user.instr_type[0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host0_o.a_user.instr_type[3] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[1:0] Yes Yes *T26,*T87,*T88 Yes T26,T87,T88 OUTPUT
tl_spi_host0_o.a_source[5:2] No No No OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[0] No No No OUTPUT
tl_spi_host0_o.a_size[1] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[0] Yes Yes *T41,*T90,*T91 Yes T41,T90,T91 OUTPUT
tl_spi_host0_o.a_opcode[1] No No No OUTPUT
tl_spi_host0_o.a_opcode[2] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host0_i.d_error No No No INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host0_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host0_i.d_sink No No No INPUT
tl_spi_host0_i.d_source[1:0] Yes Yes *T26,*T87,*T88 Yes T26,T87,T88 INPUT
tl_spi_host0_i.d_source[5:2] No No No INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[0] No No No INPUT
tl_spi_host0_i.d_size[1] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host1_o.d_ready Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host1_o.a_user.instr_type[0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host1_o.a_user.instr_type[3] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[1:0] Yes Yes *T26,*T87,*T88 Yes T26,T87,T88 OUTPUT
tl_spi_host1_o.a_source[5:2] No No No OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[0] No No No OUTPUT
tl_spi_host1_o.a_size[1] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[1:0] No No No OUTPUT
tl_spi_host1_o.a_opcode[2] Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T87,T88,T89 Yes T87,T88,T89 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host1_i.d_error No No No INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host1_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host1_i.d_data[8:0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 INPUT
tl_spi_host1_i.d_data[9] No No No INPUT
tl_spi_host1_i.d_data[10] Yes Yes *T26 Yes T26 INPUT
tl_spi_host1_i.d_data[12:11] No No No INPUT
tl_spi_host1_i.d_data[29:13] Yes Yes *T26,*T87,*T88 Yes T26,T87,T88 INPUT
tl_spi_host1_i.d_data[30] No No No INPUT
tl_spi_host1_i.d_data[31] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host1_i.d_sink No No No INPUT
tl_spi_host1_i.d_source[1:0] Yes Yes *T26,*T87,*T88 Yes T26,T87,T88 INPUT
tl_spi_host1_i.d_source[5:2] No No No INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[0] No No No INPUT
tl_spi_host1_i.d_size[1] Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T87,*T88,*T89 Yes T87,T88,T89 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T87,T88,T89 Yes T87,T88,T89 INPUT
tl_usbdev_o.d_ready Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_usbdev_o.a_user.instr_type[0] Yes Yes *T1,*T87,*T88 Yes T1,T87,T88 OUTPUT
tl_usbdev_o.a_user.instr_type[2:1] No No No OUTPUT
tl_usbdev_o.a_user.instr_type[3] Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[1:0] Yes Yes *T26,*T87,*T88 Yes T26,T87,T88 OUTPUT
tl_usbdev_o.a_source[5:2] No No No OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[0] No No No OUTPUT
tl_usbdev_o.a_size[1] Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[1:0] No No No OUTPUT
tl_usbdev_o.a_opcode[2] Yes Yes T87,T88,T92 Yes T87,T88,T92 OUTPUT
tl_usbdev_o.a_valid Yes Yes T1,T87,T88 Yes T1,T87,T88 OUTPUT
tl_usbdev_i.a_ready Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_usbdev_i.d_error No No No INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T87,T88,T92 Yes T87,T88,T92 INPUT
tl_usbdev_i.d_user.rsp_intg[1:0] Yes Yes T87,T88,T92 Yes T87,T88,T92 INPUT
tl_usbdev_i.d_user.rsp_intg[3:2] No No No INPUT
tl_usbdev_i.d_user.rsp_intg[5:4] Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_usbdev_i.d_user.rsp_intg[6] No No No INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_usbdev_i.d_sink No No No INPUT
tl_usbdev_i.d_source[1:0] Yes Yes *T26,*T87,*T88 Yes T26,T87,T88 INPUT
tl_usbdev_i.d_source[5:2] No No No INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[0] No No No INPUT
tl_usbdev_i.d_size[1] Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T1,*T87,*T88 Yes T1,T87,T88 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T1,T87,T88 Yes T1,T87,T88 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_source[5:2] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__core_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T4,T5,T6 Yes T6,T17,T18 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_sink No No No INPUT
tl_flash_ctrl__core_i.d_source[0] No No No INPUT
tl_flash_ctrl__core_i.d_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_source[5:2] No No No INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[0] No No No INPUT
tl_flash_ctrl__core_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T6,T17,T18 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_valid No No No OUTPUT
tl_flash_ctrl__prim_i.a_ready No No No INPUT
tl_flash_ctrl__prim_i.d_error No No No INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] No No No INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] No No No INPUT
tl_flash_ctrl__prim_i.d_data[31:0] No No No INPUT
tl_flash_ctrl__prim_i.d_sink No No No INPUT
tl_flash_ctrl__prim_i.d_source[5:0] No No No INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[1:0] No No No INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid No No No INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T4,T5,T30 Yes T4,T5,T30 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_source[1] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_source[5] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T4,T5,T6 Yes T6,T17,T18 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5] No No No INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_sink No No No INPUT
tl_flash_ctrl__mem_i.d_source[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_source[1] No No No INPUT
tl_flash_ctrl__mem_i.d_source[4:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_source[5] No No No INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[0] No No No INPUT
tl_flash_ctrl__mem_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_hmac_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T4,T5,T58 Yes T4,T5,T58 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T58 Yes T4,T5,T58 OUTPUT
tl_hmac_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T58 Yes T4,T5,T58 OUTPUT
tl_hmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_hmac_o.a_user.instr_type[3] Yes Yes T4,T5,T58 Yes T4,T5,T58 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T4,T5,T58 Yes T4,T5,T58 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T4,T5,T58 Yes T4,T5,T58 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[0] No No No OUTPUT
tl_hmac_o.a_source[1] Yes Yes *T4,*T5,*T58 Yes T4,T5,T58 OUTPUT
tl_hmac_o.a_source[5:2] No No No OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[0] No No No OUTPUT
tl_hmac_o.a_size[1] Yes Yes T4,T5,T58 Yes T4,T5,T58 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[0] Yes Yes *T58,*T93,*T94 Yes T58,T93,T94 OUTPUT
tl_hmac_o.a_opcode[1] No No No OUTPUT
tl_hmac_o.a_opcode[2] Yes Yes T4,T5,T58 Yes T4,T5,T58 OUTPUT
tl_hmac_o.a_valid Yes Yes T4,T5,T58 Yes T4,T5,T58 OUTPUT
tl_hmac_i.a_ready Yes Yes T4,T5,T58 Yes T4,T5,T58 INPUT
tl_hmac_i.d_error No No No INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T4,T5,T58 Yes T4,T5,T58 INPUT
tl_hmac_i.d_user.rsp_intg[1:0] Yes Yes T4,T5,T58 Yes T4,T5,T58 INPUT
tl_hmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_hmac_i.d_user.rsp_intg[5:4] Yes Yes T4,T5,T58 Yes T4,T5,T58 INPUT
tl_hmac_i.d_user.rsp_intg[6] No No No INPUT
tl_hmac_i.d_data[31:0] Yes Yes T4,T5,T58 Yes T4,T5,T58 INPUT
tl_hmac_i.d_sink No No No INPUT
tl_hmac_i.d_source[0] No No No INPUT
tl_hmac_i.d_source[1] Yes Yes *T4,*T5,*T58 Yes T4,T5,T58 INPUT
tl_hmac_i.d_source[5:2] No No No INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[0] No No No INPUT
tl_hmac_i.d_size[1] Yes Yes T4,T5,T58 Yes T4,T5,T58 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T4,*T5,*T58 Yes T4,T5,T58 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T4,T5,T58 Yes T4,T5,T58 INPUT
tl_kmac_o.d_ready Yes Yes T6,T95,T96 Yes T4,T5,T6 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T6,T95,T96 Yes T6,T95,T96 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T6,T95,T96 Yes T6,T95,T96 OUTPUT
tl_kmac_o.a_user.instr_type[0] Yes Yes *T6,*T95,*T96 Yes T6,T95,T96 OUTPUT
tl_kmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_kmac_o.a_user.instr_type[3] Yes Yes T6,T95,T96 Yes T6,T95,T96 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T6,T95,T96 Yes T6,T95,T96 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T6,T95,T96 Yes T6,T95,T96 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[1:0] Yes Yes *T76,*T97,*T6 Yes T76,T97,T6 OUTPUT
tl_kmac_o.a_source[5:2] No No No OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[0] No No No OUTPUT
tl_kmac_o.a_size[1] Yes Yes T6,T95,T96 Yes T6,T95,T96 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[0] Yes Yes *T95,*T96,*T98 Yes T95,T96,T98 OUTPUT
tl_kmac_o.a_opcode[1] No No No OUTPUT
tl_kmac_o.a_opcode[2] Yes Yes T6,T95,T96 Yes T6,T95,T96 OUTPUT
tl_kmac_o.a_valid Yes Yes T6,T95,T96 Yes T6,T95,T96 OUTPUT
tl_kmac_i.a_ready Yes Yes T6,T95,T96 Yes T6,T95,T96 INPUT
tl_kmac_i.d_error No No No INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T6,T95,T96 Yes T6,T95,T96 INPUT
tl_kmac_i.d_user.rsp_intg[1:0] Yes Yes T6,T95,T96 Yes T6,T95,T96 INPUT
tl_kmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_kmac_i.d_user.rsp_intg[5:4] Yes Yes T95,T96,T18 Yes T6,T95,T96 INPUT
tl_kmac_i.d_user.rsp_intg[6] No No No INPUT
tl_kmac_i.d_data[31:0] Yes Yes T6,T95,T96 Yes T95,T96,T18 INPUT
tl_kmac_i.d_sink No No No INPUT
tl_kmac_i.d_source[1:0] Yes Yes *T76,*T97,*T6 Yes T76,T97,T6 INPUT
tl_kmac_i.d_source[5:2] No No No INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[0] No No No INPUT
tl_kmac_i.d_size[1] Yes Yes T95,T96,T18 Yes T6,T95,T96 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T6,*T95,*T96 Yes T95,T96,T18 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T6,T95,T96 Yes T6,T95,T96 INPUT
tl_aes_o.d_ready Yes Yes T6,T17,T18 Yes T4,T5,T6 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T99,T100,T101 Yes T99,T100,T101 OUTPUT
tl_aes_o.a_user.cmd_intg[0] Yes Yes *T99,*T100,*T101 Yes T99,T100,T101 OUTPUT
tl_aes_o.a_user.cmd_intg[1] No No No OUTPUT
tl_aes_o.a_user.cmd_intg[6:2] Yes Yes T99,T100,T101 Yes T99,T100,T101 OUTPUT
tl_aes_o.a_user.instr_type[0] Yes Yes *T99,*T100,*T101 Yes T99,T100,T101 OUTPUT
tl_aes_o.a_user.instr_type[2:1] No No No OUTPUT
tl_aes_o.a_user.instr_type[3] Yes Yes T99,T100,T101 Yes T99,T100,T101 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T99,T100,T101 Yes T99,T100,T101 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T99,T100,T101 Yes T99,T100,T101 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[0] No No No OUTPUT
tl_aes_o.a_source[1] Yes Yes *T99,*T100,*T101 Yes T99,T100,T101 OUTPUT
tl_aes_o.a_source[5:2] No No No OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[0] No No No OUTPUT
tl_aes_o.a_size[1] Yes Yes T99,T100,T101 Yes T99,T100,T101 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[1:0] No No No OUTPUT
tl_aes_o.a_opcode[2] Yes Yes T99,T100,T101 Yes T99,T100,T101 OUTPUT
tl_aes_o.a_valid Yes Yes T99,T100,T101 Yes T99,T100,T101 OUTPUT
tl_aes_i.a_ready Yes Yes T99,T100,T101 Yes T99,T100,T101 INPUT
tl_aes_i.d_error No No No INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T99,T100,T101 Yes T99,T100,T101 INPUT
tl_aes_i.d_user.rsp_intg[1:0] Yes Yes T99,T100,T101 Yes T99,T100,T101 INPUT
tl_aes_i.d_user.rsp_intg[3:2] No No No INPUT
tl_aes_i.d_user.rsp_intg[5:4] Yes Yes *T102,*T103,*T104 Yes T99,T100,T101 INPUT
tl_aes_i.d_user.rsp_intg[6] No No No INPUT
tl_aes_i.d_data[31:0] Yes Yes T100,T105,T106 Yes T99,T100,T101 INPUT
tl_aes_i.d_sink No No No INPUT
tl_aes_i.d_source[0] No No No INPUT
tl_aes_i.d_source[1] Yes Yes *T99,*T100,*T101 Yes T99,T100,T101 INPUT
tl_aes_i.d_source[5:2] No No No INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[0] No No No INPUT
tl_aes_i.d_size[1] Yes Yes T102,T103,T104 Yes T99,T100,T101 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T99,*T100,*T101 Yes T99,T100,T101 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T99,T100,T101 Yes T99,T100,T101 INPUT
tl_entropy_src_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1] No No No OUTPUT
tl_entropy_src_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[0] No No No OUTPUT
tl_entropy_src_o.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_source[5:2] No No No OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[0] No No No OUTPUT
tl_entropy_src_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[1:0] No No No OUTPUT
tl_entropy_src_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_error No No No INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2] No No No INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4] Yes Yes T6,*T17,*T18 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_user.rsp_intg[6] No No No INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_sink No No No INPUT
tl_entropy_src_i.d_source[0] No No No INPUT
tl_entropy_src_i.d_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_source[5:2] No No No INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[0] No No No INPUT
tl_entropy_src_i.d_size[1] Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T6,*T99,*T107 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.instr_type[2:1] No No No OUTPUT
tl_csrng_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[0] No No No OUTPUT
tl_csrng_o.a_source[1] Yes Yes *T6,*T99,*T107 Yes T6,T99,T107 OUTPUT
tl_csrng_o.a_source[5:2] No No No OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[0] No No No OUTPUT
tl_csrng_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[1:0] No No No OUTPUT
tl_csrng_o.a_opcode[2] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_csrng_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_i.d_error No No No INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 INPUT
tl_csrng_i.d_user.rsp_intg[1:0] Yes Yes T6,T17,*T18 Yes T4,T5,T6 INPUT
tl_csrng_i.d_user.rsp_intg[3:2] No No No INPUT
tl_csrng_i.d_user.rsp_intg[5:4] Yes Yes T6,*T17,*T18 Yes T4,T5,T6 INPUT
tl_csrng_i.d_user.rsp_intg[6] No No No INPUT
tl_csrng_i.d_data[31:0] Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
tl_csrng_i.d_sink No No No INPUT
tl_csrng_i.d_source[0] No No No INPUT
tl_csrng_i.d_source[1] Yes Yes *T6,*T99,*T107 Yes T6,T99,T107 INPUT
tl_csrng_i.d_source[5:2] No No No INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[0] No No No INPUT
tl_csrng_i.d_size[1] Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T6,*T99,*T107 Yes T6,T99,T107 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn0_o.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn0_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[0] No No No OUTPUT
tl_edn0_o.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_source[5:2] No No No OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[0] No No No OUTPUT
tl_edn0_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[1:0] No No No OUTPUT
tl_edn0_o.a_opcode[2] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn0_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_i.d_error No No No INPUT
tl_edn0_i.d_user.data_intg[0] Yes Yes *T6,*T99,*T107 Yes T6,T99,T107 INPUT
tl_edn0_i.d_user.data_intg[1] No No No INPUT
tl_edn0_i.d_user.data_intg[6:2] Yes Yes T6,T99,T107 Yes T6,T99,T107 INPUT
tl_edn0_i.d_user.rsp_intg[1:0] Yes Yes T6,T17,*T18 Yes T4,T5,T6 INPUT
tl_edn0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn0_i.d_user.rsp_intg[5:4] Yes Yes T6,*T17,*T18 Yes T4,T5,T6 INPUT
tl_edn0_i.d_user.rsp_intg[6] No No No INPUT
tl_edn0_i.d_data[31:0] Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
tl_edn0_i.d_sink No No No INPUT
tl_edn0_i.d_source[0] No No No INPUT
tl_edn0_i.d_source[1] Yes Yes *T6,*T17,*T18 Yes T4,T5,T6 INPUT
tl_edn0_i.d_source[5:2] No No No INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[0] No No No INPUT
tl_edn0_i.d_size[1] Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T6,*T99,*T107 Yes T6,T99,T107 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn1_o.d_ready Yes Yes T6,T17,T18 Yes T4,T5,T6 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn1_o.a_user.cmd_intg[0] Yes Yes *T6,*T99,*T107 Yes T6,T99,T107 OUTPUT
tl_edn1_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn1_o.a_user.instr_type[0] Yes Yes *T6,*T99,*T107 Yes T6,T99,T107 OUTPUT
tl_edn1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn1_o.a_user.instr_type[3] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[0] No No No OUTPUT
tl_edn1_o.a_source[1] Yes Yes *T6,*T99,*T107 Yes T6,T99,T107 OUTPUT
tl_edn1_o.a_source[5:2] No No No OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[0] No No No OUTPUT
tl_edn1_o.a_size[1] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[1:0] No No No OUTPUT
tl_edn1_o.a_opcode[2] Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn1_o.a_valid Yes Yes T6,T99,T107 Yes T6,T99,T107 OUTPUT
tl_edn1_i.a_ready Yes Yes T6,T99,T107 Yes T6,T99,T107 INPUT
tl_edn1_i.d_error No No No INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 INPUT
tl_edn1_i.d_user.rsp_intg[1:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 INPUT
tl_edn1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn1_i.d_user.rsp_intg[5:4] Yes Yes *T108,*T109,*T110 Yes T6,T99,T107 INPUT
tl_edn1_i.d_user.rsp_intg[6] No No No INPUT
tl_edn1_i.d_data[31:0] Yes Yes T6,T99,T107 Yes T6,T99,T107 INPUT
tl_edn1_i.d_sink No No No INPUT
tl_edn1_i.d_source[0] No No No INPUT
tl_edn1_i.d_source[1] Yes Yes *T6,*T99,*T107 Yes T6,T99,T107 INPUT
tl_edn1_i.d_source[5:2] No No No INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[0] No No No INPUT
tl_edn1_i.d_size[1] Yes Yes T108,T109,T110 Yes T6,T99,T107 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T6,*T99,*T107 Yes T6,T99,T107 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T6,T99,T107 Yes T6,T99,T107 INPUT
tl_rv_plic_o.d_ready Yes Yes T6,T30,T17 Yes T4,T5,T6 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
tl_rv_plic_o.a_user.instr_type[0] Yes Yes *T30,*T31,*T32 Yes T30,T31,T32 OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_plic_o.a_user.instr_type[3] Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[1:0] Yes Yes *T26,*T30,*T31 Yes T26,T30,T31 OUTPUT
tl_rv_plic_o.a_source[5:2] No No No OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[0] No No No OUTPUT
tl_rv_plic_o.a_size[1] Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[1:0] No No No OUTPUT
tl_rv_plic_o.a_opcode[2] Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
tl_rv_plic_i.d_error No No No INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4] Yes Yes T19,T1,*T86 Yes T30,T31,T32 INPUT
tl_rv_plic_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
tl_rv_plic_i.d_sink No No No INPUT
tl_rv_plic_i.d_source[1:0] Yes Yes *T26,*T30,*T31 Yes T26,T30,T31 INPUT
tl_rv_plic_i.d_source[5:2] No No No INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[0] No No No INPUT
tl_rv_plic_i.d_size[1] Yes Yes T19,T1,T86 Yes T30,T31,T32 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T30,*T31,*T32 Yes T30,T31,T32 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
tl_otbn_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T4,T5,T99 Yes T4,T5,T99 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T99 Yes T4,T5,T99 OUTPUT
tl_otbn_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T99 Yes T4,T5,T99 OUTPUT
tl_otbn_o.a_user.instr_type[2:1] No No No OUTPUT
tl_otbn_o.a_user.instr_type[3] Yes Yes T4,T5,T99 Yes T4,T5,T99 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T4,T5,T99 Yes T4,T5,T99 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T4,T5,T99 Yes T4,T5,T99 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[1:0] Yes Yes *T22,*T24,*T76 Yes T22,T24,T76 OUTPUT
tl_otbn_o.a_source[5:2] No No No OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[0] No No No OUTPUT
tl_otbn_o.a_size[1] Yes Yes T4,T5,T99 Yes T4,T5,T99 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[1:0] No No No OUTPUT
tl_otbn_o.a_opcode[2] Yes Yes T4,T5,T99 Yes T4,T5,T99 OUTPUT
tl_otbn_o.a_valid Yes Yes T4,T5,T99 Yes T4,T5,T99 OUTPUT
tl_otbn_i.a_ready Yes Yes T4,T5,T99 Yes T4,T5,T99 INPUT
tl_otbn_i.d_error No No No INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T4,T5,T99 Yes T4,T5,T99 INPUT
tl_otbn_i.d_user.rsp_intg[1:0] Yes Yes T4,T5,T99 Yes T4,T5,T99 INPUT
tl_otbn_i.d_user.rsp_intg[3:2] No No No INPUT
tl_otbn_i.d_user.rsp_intg[5:4] Yes Yes T4,T5,T99 Yes T4,T5,T99 INPUT
tl_otbn_i.d_user.rsp_intg[6] No No No INPUT
tl_otbn_i.d_data[31:0] Yes Yes T4,T5,T99 Yes T4,T5,T99 INPUT
tl_otbn_i.d_sink No No No INPUT
tl_otbn_i.d_source[1:0] Yes Yes *T22,*T24,*T76 Yes T22,T24,T76 INPUT
tl_otbn_i.d_source[5:2] No No No INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[0] No No No INPUT
tl_otbn_i.d_size[1] Yes Yes T4,T5,T99 Yes T4,T5,T99 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T4,*T5,*T99 Yes T4,T5,T99 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T4,T5,T99 Yes T4,T5,T99 INPUT
tl_keymgr_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.cmd_intg[1] No No No OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.instr_type[2:1] No No No OUTPUT
tl_keymgr_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T4,T6,T18 Yes T4,T6,T18 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[0] No No No OUTPUT
tl_keymgr_o.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_source[5:2] No No No OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[0] No No No OUTPUT
tl_keymgr_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[1:0] No No No OUTPUT
tl_keymgr_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_keymgr_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_keymgr_i.d_error No No No INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T6,T18,T111 Yes T6,T18,T111 INPUT
tl_keymgr_i.d_user.rsp_intg[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_keymgr_i.d_user.rsp_intg[3:2] No No No INPUT
tl_keymgr_i.d_user.rsp_intg[5:4] Yes Yes T18,T34,T112 Yes T4,T5,T6 INPUT
tl_keymgr_i.d_user.rsp_intg[6] No No No INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_keymgr_i.d_sink No No No INPUT
tl_keymgr_i.d_source[0] No No No INPUT
tl_keymgr_i.d_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_keymgr_i.d_source[5:2] No No No INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[0] No No No INPUT
tl_keymgr_i.d_size[1] Yes Yes T18,T34,T112 Yes T4,T5,T6 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1:0] Yes Yes *T25,*T4,*T5 Yes T25,T4,T5 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_error No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T4,T5,T30 Yes T4,T5,T30 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4] Yes Yes T6,T17,*T18 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T4,T5,T30 Yes T4,T5,T30 INPUT
tl_rv_core_ibex__cfg_i.d_sink No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[0] No No Yes T25 INPUT
tl_rv_core_ibex__cfg_i.d_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_size[1] Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T17 Yes T4,T5,T17 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2] Yes Yes T17,T113,T114 Yes T17,T113,T114 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T17 Yes T4,T5,T17 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3] Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0] Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0] Yes Yes *T26,*T4,*T5 Yes T26,T4,T5 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1] Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2] Yes Yes T17,T113,T114 Yes T17,T113,T114 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T4,T5,T17 Yes T4,T5,T17 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
tl_sram_ctrl_main__regs_i.d_error No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0] Yes Yes T115,T116,T26 Yes T115,T116,T26 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0] Yes Yes T17,T33,T113 Yes T4,T5,T17 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4] Yes Yes T17,*T33,T113 Yes T4,T5,T17 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T17,T33,T113 Yes T4,T5,T17 INPUT
tl_sram_ctrl_main__regs_i.d_sink No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[1:0] Yes Yes *T26,*T17,*T33 Yes T26,T4,T5 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__regs_i.d_size[1] Yes Yes T17,T33,T113 Yes T4,T5,T17 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T17,*T113,*T114 Yes T17,T113,T114 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T4,T5,T17 Yes T4,T5,T17 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T4,T5,T6 Yes T6,T17,T18 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3] No No No INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_sink No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_source[5] No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__ram_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%