Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.73 89.73

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_timer 89.73 89.73



Module Instance : tb.dut.top_earlgrey.u_rv_timer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.73 89.73


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.73 89.73


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.12 88.53 87.83 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : rv_timer
TotalCoveredPercent
Totals 30 22 73.33
Total Bits 292 262 89.73
Total Bits 0->1 146 131 89.73
Total Bits 1->0 146 131 89.73

Ports 30 22 73.33
Port Bits 292 262 89.73
Port Bits 0->1 146 131 89.73
Port Bits 1->0 146 131 89.73

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T6,T17,T18 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T143,T257,T258 Yes T143,T257,T258 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T143,T257,T258 Yes T143,T257,T258 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[8:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[19:9] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T22,*T23,*T20 Yes T22,T23,T20 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T22,*T24,*T76 Yes T22,T24,T76 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T143,T257,T258 Yes T143,T257,T258 INPUT
tl_o.a_ready Yes Yes T143,T257,T258 Yes T143,T257,T258 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T257,T258,T330 Yes T257,T258,T330 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T143,T257,T258 Yes T143,T257,T258 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T26,*T331,*T332 Yes T143,T257,T258 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T143,T257,T258 Yes T143,T257,T258 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T26,*T143,*T257 Yes T26,T143,T257 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T26,T331,T332 Yes T143,T257,T258 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T143,*T257,*T258 Yes T143,T257,T258 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T143,T257,T258 Yes T143,T257,T258 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_rx_i[0].ping_n Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_rx_i[0].ping_p Yes Yes T27,T29,T128 Yes T27,T29,T128 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T27,T29,T128 Yes T27,T29,T128 OUTPUT
intr_timer_expired_hart0_timer0_o Yes Yes T257,T258,T259 Yes T257,T258,T259 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%