Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.13			92.13

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rom_ctrl	94.69			94.69

---

Module Instance : tb.dut.top_earlgrey.u_rom_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.69			94.69

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.69			94.69

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.12	88.53		87.83			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	65	38	58.46
Total Bits	2808	2587	92.13
Total Bits 0->1	1404	1294	92.17
Total Bits 1->0	1404	1293	92.09

Ports	65	38	58.46
Port Bits	2808	2587	92.13
Port Bits 0->1	1404	1294	92.17
Port Bits 1->0	1404	1293	92.09

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_address[1:0]	No	No		No		INPUT
rom_tl_i.a_address[15:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_address[31:16]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_source[5]	No	No		No		INPUT
rom_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_size[0]	No	No		No		INPUT
rom_tl_i.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[1:0]	No	No		No		INPUT
rom_tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_error	No	No		No		OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
rom_tl_o.d_user.rsp_intg[4]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_user.rsp_intg[6:5]	No	No		No		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_sink	No	No		No		OUTPUT
rom_tl_o.d_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_source[5]	No	No		No		OUTPUT
rom_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_size[0]	No	No		No		OUTPUT
rom_tl_o.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	No	No		No		OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
regs_tl_i.a_user.data_intg[2]	No	No		No		INPUT
regs_tl_i.a_user.data_intg[5:3]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_user.data_intg[6]	No	No		No		INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
regs_tl_i.a_data[31:1]	No	No		No		INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[6:2]	Yes	Yes	*T81,T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:17]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[0]	No	No		No		INPUT
regs_tl_i.a_source[1]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_source[5:2]	No	No		No		INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[0]	No	No		No		INPUT
regs_tl_i.a_size[1]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[1:0]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_valid	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_o.a_ready	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	OUTPUT
regs_tl_o.d_user.rsp_intg[0]	No	No		Yes	T78,T79,T80	OUTPUT
regs_tl_o.d_user.rsp_intg[1]	No	Yes	*T78,*T79,*T80	No		OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T82,T84,T85	Yes	T82,T78,T84	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[0]	No	No		No		OUTPUT
regs_tl_o.d_source[1]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T27,T146,T29	Yes	T27,T146,T29	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T27,T146,T29	Yes	T27,T146,T29	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T4,T5,T6	Yes	T6,T17,T18	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T4,T5,T6	Yes	T6,T17,T18	OUTPUT
keymgr_data_o.valid	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T22,T191,T233	Yes	T329,T22,T123	OUTPUT
kmac_data_i.error	No	No		Yes	T70,T190,T193	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T4,T5,T71	Yes	T4,T5,T71	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T4,T5,T71	Yes	T4,T5,T71	INPUT
kmac_data_i.done	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
kmac_data_i.ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
kmac_data_o.last	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rom_ctrl

	Total	Covered	Percent
Totals	62	39	62.90
Total Bits	2732	2587	94.69
Total Bits 0->1	1366	1294	94.73
Total Bits 1->0	1366	1293	94.66

Ports	62	39	62.90
Port Bits	2732	2587	94.69
Port Bits 0->1	1366	1294	94.73
Port Bits 1->0	1366	1293	94.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
rom_cfg_i.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_address[1:0]	No	No		No		INPUT
rom_tl_i.a_address[15:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_address[31:16]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_source[5]	No	No		No		INPUT
rom_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_size[0]	No	No		No		INPUT
rom_tl_i.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[1:0]	No	No		No		INPUT
rom_tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rom_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_error	No	No		No		OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
rom_tl_o.d_user.rsp_intg[4]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_user.rsp_intg[6:5]	No	No		No		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_sink	No	No		No		OUTPUT
rom_tl_o.d_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_source[5]	No	No		No		OUTPUT
rom_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_size[0]	No	No		No		OUTPUT
rom_tl_o.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	No	No		No		OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
regs_tl_i.a_user.data_intg[2]	No	No		No		INPUT
regs_tl_i.a_user.data_intg[5:3]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_user.data_intg[6]	No	No		No		INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
regs_tl_i.a_data[31:1]	No	No		No		INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[6:2]	Yes	Yes	*T81,T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:17]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[0]	No	No		No		INPUT
regs_tl_i.a_source[1]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_source[5:2]	No	No		No		INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[0]	No	No		No		INPUT
regs_tl_i.a_size[1]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[1:0]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_i.a_valid	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
regs_tl_o.a_ready	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T82,T84,T85	Yes	T82,T84,T85	OUTPUT
regs_tl_o.d_user.rsp_intg[0]	No	No		Yes	T78,T79,T80	OUTPUT
regs_tl_o.d_user.rsp_intg[1]	No	Yes	*T78,*T79,*T80	No		OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T82,T84,T85	Yes	T82,T78,T84	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[0]	No	No		No		OUTPUT
regs_tl_o.d_source[1]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T27,T146,T29	Yes	T27,T146,T29	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T27,T29,T128	Yes	T27,T29,T128	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T27,T146,T29	Yes	T27,T146,T29	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T4,T5,T6	Yes	T6,T17,T18	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T4,T5,T6	Yes	T6,T17,T18	OUTPUT
keymgr_data_o.valid	Yes	Yes	T6,T17,T18	Yes	T4,T5,T6	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T22,T191,T233	Yes	T329,T22,T123	OUTPUT
kmac_data_i.error	No	No		Yes	T70,T190,T193	INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T4,T5,T71	Yes	T4,T5,T71	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T4,T5,T71	Yes	T4,T5,T71	INPUT
kmac_data_i.done	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
kmac_data_i.ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
kmac_data_o.last	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_o.strb[7:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
kmac_data_o.data[38:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
kmac_data_o.data[63:39]	Excluded	Excluded		Excluded		OUTPUT	[UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
kmac_data_o.valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range