Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T194,T297,T298
0	1	Covered	T194,T297,T298
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T194,T297,T298
1	Covered	T194,T297,T298

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T194,T297,T298
1	Covered	T194,T297,T298

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T194,T297,T298
1	1	Covered	T194,T297,T298

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T194,T297,T298
1	0	Covered	T194,T297,T298
1	1	Covered	T194,T297,T298

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T194,T297,T298

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T194,T297,T298
0	Covered	T194,T297,T298

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T194,T297,T298
0	Covered	T194,T297,T298

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	983141422	964744638	0	0
CheckNGreaterZero_A	2002	2002	0	0
GntImpliesReady_A	983141422	8443	0	0
GntImpliesValid_A	983141422	8443	0	0
GrantKnown_A	983141422	964744638	0	0
IdxKnown_A	983141422	964744638	0	0
IndexIsCorrect_A	983141422	8443	0	0
NoReadyValidNoGrant_A	983141422	0	0	0
Priority_A	983141422	8443	0	0
ReadyAndValidImplyGrant_A	983141422	8443	0	0
ReqAndReadyImplyGrant_A	983141422	8443	0	0
ReqImpliesValid_A	983141422	8443	0	0
ValidKnown_A	983141422	964744638	0	0
gen_data_port_assertion.DataFlow_A	983141422	8443	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	964744638	0	0
T4	284996	284986	0	0
T5	245066	245052	0	0
T6	1475442	1475230	0	0
T17	429664	429432	0	0
T30	567998	567874	0	0
T31	323564	323454	0	0
T58	224788	224686	0	0
T93	945542	945440	0	0
T95	186290	186174	0	0
T96	191442	191332	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2002	2002	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T30	2	2	0	0
T31	2	2	0	0
T58	2	2	0	0
T93	2	2	0	0
T95	2	2	0	0
T96	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	8443	0	0
T59	183734	0	0	0
T121	1030264	0	0	0
T122	597174	0	0	0
T167	484312	0	0	0
T194	177016	2822	0	0
T199	310078	0	0	0
T297	0	2802	0	0
T298	0	2819	0	0
T299	796374	0	0	0
T300	1051926	0	0	0
T301	76622	0	0	0
T302	1160550	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	8443	0	0
T59	183734	0	0	0
T121	1030264	0	0	0
T122	597174	0	0	0
T167	484312	0	0	0
T194	177016	2822	0	0
T199	310078	0	0	0
T297	0	2802	0	0
T298	0	2819	0	0
T299	796374	0	0	0
T300	1051926	0	0	0
T301	76622	0	0	0
T302	1160550	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	964744638	0	0
T4	284996	284986	0	0
T5	245066	245052	0	0
T6	1475442	1475230	0	0
T17	429664	429432	0	0
T30	567998	567874	0	0
T31	323564	323454	0	0
T58	224788	224686	0	0
T93	945542	945440	0	0
T95	186290	186174	0	0
T96	191442	191332	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	964744638	0	0
T4	284996	284986	0	0
T5	245066	245052	0	0
T6	1475442	1475230	0	0
T17	429664	429432	0	0
T30	567998	567874	0	0
T31	323564	323454	0	0
T58	224788	224686	0	0
T93	945542	945440	0	0
T95	186290	186174	0	0
T96	191442	191332	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	8443	0	0
T59	183734	0	0	0
T121	1030264	0	0	0
T122	597174	0	0	0
T167	484312	0	0	0
T194	177016	2822	0	0
T199	310078	0	0	0
T297	0	2802	0	0
T298	0	2819	0	0
T299	796374	0	0	0
T300	1051926	0	0	0
T301	76622	0	0	0
T302	1160550	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	8443	0	0
T59	183734	0	0	0
T121	1030264	0	0	0
T122	597174	0	0	0
T167	484312	0	0	0
T194	177016	2822	0	0
T199	310078	0	0	0
T297	0	2802	0	0
T298	0	2819	0	0
T299	796374	0	0	0
T300	1051926	0	0	0
T301	76622	0	0	0
T302	1160550	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	8443	0	0
T59	183734	0	0	0
T121	1030264	0	0	0
T122	597174	0	0	0
T167	484312	0	0	0
T194	177016	2822	0	0
T199	310078	0	0	0
T297	0	2802	0	0
T298	0	2819	0	0
T299	796374	0	0	0
T300	1051926	0	0	0
T301	76622	0	0	0
T302	1160550	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	8443	0	0
T59	183734	0	0	0
T121	1030264	0	0	0
T122	597174	0	0	0
T167	484312	0	0	0
T194	177016	2822	0	0
T199	310078	0	0	0
T297	0	2802	0	0
T298	0	2819	0	0
T299	796374	0	0	0
T300	1051926	0	0	0
T301	76622	0	0	0
T302	1160550	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	8443	0	0
T59	183734	0	0	0
T121	1030264	0	0	0
T122	597174	0	0	0
T167	484312	0	0	0
T194	177016	2822	0	0
T199	310078	0	0	0
T297	0	2802	0	0
T298	0	2819	0	0
T299	796374	0	0	0
T300	1051926	0	0	0
T301	76622	0	0	0
T302	1160550	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	964744638	0	0
T4	284996	284986	0	0
T5	245066	245052	0	0
T6	1475442	1475230	0	0
T17	429664	429432	0	0
T30	567998	567874	0	0
T31	323564	323454	0	0
T58	224788	224686	0	0
T93	945542	945440	0	0
T95	186290	186174	0	0
T96	191442	191332	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983141422	8443	0	0
T59	183734	0	0	0
T121	1030264	0	0	0
T122	597174	0	0	0
T167	484312	0	0	0
T194	177016	2822	0	0
T199	310078	0	0	0
T297	0	2802	0	0
T298	0	2819	0	0
T299	796374	0	0	0
T300	1051926	0	0	0
T301	76622	0	0	0
T302	1160550	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T194,T297,T298
0	1	Covered	T194,T297,T298
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T194,T297,T298
1	Covered	T194,T297,T298

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T194,T297,T298
1	Covered	T194,T297,T298

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T194,T297,T298
1	1	Covered	T194,T297,T298

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T194,T297,T298
1	0	Covered	T194,T297,T298
1	1	Covered	T194,T297,T298

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T194,T297,T298

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T194,T297,T298
0	Covered	T194,T297,T298

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T194,T297,T298
0	Covered	T194,T297,T298

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	491570711	482372319	0	0
CheckNGreaterZero_A	1001	1001	0	0
GntImpliesReady_A	491570711	5258	0	0
GntImpliesValid_A	491570711	5258	0	0
GrantKnown_A	491570711	482372319	0	0
IdxKnown_A	491570711	482372319	0	0
IndexIsCorrect_A	491570711	5258	0	0
NoReadyValidNoGrant_A	491570711	0	0	0
Priority_A	491570711	5258	0	0
ReadyAndValidImplyGrant_A	491570711	5258	0	0
ReqAndReadyImplyGrant_A	491570711	5258	0	0
ReqImpliesValid_A	491570711	5258	0	0
ValidKnown_A	491570711	482372319	0	0
gen_data_port_assertion.DataFlow_A	491570711	5258	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	482372319	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	5258	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1759	0	0
T199	155039	0	0	0
T297	0	1741	0	0
T298	0	1758	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	5258	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1759	0	0
T199	155039	0	0	0
T297	0	1741	0	0
T298	0	1758	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	482372319	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	482372319	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	5258	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1759	0	0
T199	155039	0	0	0
T297	0	1741	0	0
T298	0	1758	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	5258	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1759	0	0
T199	155039	0	0	0
T297	0	1741	0	0
T298	0	1758	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	5258	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1759	0	0
T199	155039	0	0	0
T297	0	1741	0	0
T298	0	1758	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	5258	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1759	0	0
T199	155039	0	0	0
T297	0	1741	0	0
T298	0	1758	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	5258	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1759	0	0
T199	155039	0	0	0
T297	0	1741	0	0
T298	0	1758	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	482372319	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	5258	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1759	0	0
T199	155039	0	0	0
T297	0	1741	0	0
T298	0	1758	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T194,T297,T298
0	1	Covered	T194,T297,T298
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T194,T297,T298
1	Covered	T194,T297,T298

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T194,T297,T298
1	Covered	T194,T297,T298

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T194,T297,T298
1	1	Covered	T194,T297,T298

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T194,T297,T298
1	0	Covered	T194,T297,T298
1	1	Covered	T194,T297,T298

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T194,T297,T298

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T194,T297,T298
0	Covered	T194,T297,T298

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T194,T297,T298
0	Covered	T194,T297,T298

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	491570711	482372319	0	0
CheckNGreaterZero_A	1001	1001	0	0
GntImpliesReady_A	491570711	3185	0	0
GntImpliesValid_A	491570711	3185	0	0
GrantKnown_A	491570711	482372319	0	0
IdxKnown_A	491570711	482372319	0	0
IndexIsCorrect_A	491570711	3185	0	0
NoReadyValidNoGrant_A	491570711	0	0	0
Priority_A	491570711	3185	0	0
ReadyAndValidImplyGrant_A	491570711	3185	0	0
ReqAndReadyImplyGrant_A	491570711	3185	0	0
ReqImpliesValid_A	491570711	3185	0	0
ValidKnown_A	491570711	482372319	0	0
gen_data_port_assertion.DataFlow_A	491570711	3185	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	482372319	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T58	1	1	0	0
T93	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	3185	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1063	0	0
T199	155039	0	0	0
T297	0	1061	0	0
T298	0	1061	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	3185	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1063	0	0
T199	155039	0	0	0
T297	0	1061	0	0
T298	0	1061	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	482372319	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	482372319	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	3185	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1063	0	0
T199	155039	0	0	0
T297	0	1061	0	0
T298	0	1061	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	3185	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1063	0	0
T199	155039	0	0	0
T297	0	1061	0	0
T298	0	1061	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	3185	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1063	0	0
T199	155039	0	0	0
T297	0	1061	0	0
T298	0	1061	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	3185	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1063	0	0
T199	155039	0	0	0
T297	0	1061	0	0
T298	0	1061	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	3185	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1063	0	0
T199	155039	0	0	0
T297	0	1061	0	0
T298	0	1061	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	482372319	0	0
T4	142498	142493	0	0
T5	122533	122526	0	0
T6	737721	737615	0	0
T17	214832	214716	0	0
T30	283999	283937	0	0
T31	161782	161727	0	0
T58	112394	112343	0	0
T93	472771	472720	0	0
T95	93145	93087	0	0
T96	95721	95666	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491570711	3185	0	0
T59	91867	0	0	0
T121	515132	0	0	0
T122	298587	0	0	0
T167	242156	0	0	0
T194	88508	1063	0	0
T199	155039	0	0	0
T297	0	1061	0	0
T298	0	1061	0	0
T299	398187	0	0	0
T300	525963	0	0	0
T301	38311	0	0	0
T302	580275	0	0	0