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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.45 45.45 36.36 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.58 68.00 30.00 83.33 25.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.40 98.55 67.04 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 51.82 80.00 27.27 100.00 0.00
u_src_to_dst_req 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.45 45.45 36.36 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.58 68.00 30.00 83.33 25.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.40 98.55 67.04 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 51.82 80.00 27.27 100.00 0.00
u_src_to_dst_req 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.45 45.45 36.36 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.58 68.00 30.00 83.33 25.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.40 98.55 67.04 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 51.82 80.00 27.27 100.00 0.00
u_src_to_dst_req 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.45 45.45 36.36 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.58 68.00 30.00 83.33 25.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.40 98.55 67.04 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 51.82 80.00 27.27 100.00 0.00
u_src_to_dst_req 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.45 45.45 36.36 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.58 68.00 30.00 83.33 25.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.40 98.55 67.04 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 51.82 80.00 27.27 100.00 0.00
u_src_to_dst_req 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.45 45.45 36.36 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.58 68.00 30.00 83.33 25.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.40 98.55 67.04 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 51.82 80.00 27.27 100.00 0.00
u_src_to_dst_req 54.33 92.31 25.00 100.00 0.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.34 95.49 76.06 89.83 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.40 98.55 67.04 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 87.33 93.88 69.39 86.05 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc
Line No.TotalCoveredPercent
TOTAL221045.45
CONT_ASSIGN65100.00
ALWAYS716466.67
CONT_ASSIGN85100.00
CONT_ASSIGN109100.00
ALWAYS1159555.56
CONT_ASSIGN15011100.00
CONT_ASSIGN155100.00
CONT_ASSIGN156100.00
CONT_ASSIGN200100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 0 1
71 1 1
72 1 1
73 1 1
74 0 1
75 1 1
76 0 1
MISSING_ELSE
85 0 1
109 0 1
115 1 1
116 1 1
117 1 1
118 1 1
123 0 1
124 0 1
125 1 1
134 0 1
135 0 1
MISSING_ELSE
150 1 1
155 0 1
156 0 1
200 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc
TotalCoveredPercent
Conditions11436.36
Logical11436.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc
Line No.TotalCoveredPercent
Branches 8 4 50.00
IF 71 4 2 50.00
IF 115 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 122639056 0 0 0
DstReqKnown_A 1562074 1370371 0 0
SrcAckBusyChk_A 122639056 0 0 0
SrcBusyKnown_A 122639056 121971811 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1562074 1370371 0 0
T4 3088 2916 0 0
T5 2718 2544 0 0
T6 1878 1705 0 0
T17 924 749 0 0
T30 806 632 0 0
T31 688 516 0 0
T58 449 278 0 0
T93 1108 936 0 0
T95 544 370 0 0
T96 377 205 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 121971811 0 0
T4 342881 342388 0 0
T5 294896 294466 0 0
T6 178386 177811 0 0
T17 52694 52309 0 0
T30 69037 68530 0 0
T31 43673 43325 0 0
T58 27829 27345 0 0
T93 114897 113841 0 0
T95 31068 30701 0 0
T96 24130 23342 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc
Line No.TotalCoveredPercent
TOTAL221045.45
CONT_ASSIGN65100.00
ALWAYS716466.67
CONT_ASSIGN85100.00
CONT_ASSIGN109100.00
ALWAYS1159555.56
CONT_ASSIGN15011100.00
CONT_ASSIGN155100.00
CONT_ASSIGN156100.00
CONT_ASSIGN200100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 0 1
71 1 1
72 1 1
73 1 1
74 0 1
75 1 1
76 0 1
MISSING_ELSE
85 0 1
109 0 1
115 1 1
116 1 1
117 1 1
118 1 1
123 0 1
124 0 1
125 1 1
134 0 1
135 0 1
MISSING_ELSE
150 1 1
155 0 1
156 0 1
200 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc
TotalCoveredPercent
Conditions11436.36
Logical11436.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc
Line No.TotalCoveredPercent
Branches 8 4 50.00
IF 71 4 2 50.00
IF 115 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 122639056 0 0 0
DstReqKnown_A 1562074 1370371 0 0
SrcAckBusyChk_A 122639056 0 0 0
SrcBusyKnown_A 122639056 121971811 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1562074 1370371 0 0
T4 3088 2916 0 0
T5 2718 2544 0 0
T6 1878 1705 0 0
T17 924 749 0 0
T30 806 632 0 0
T31 688 516 0 0
T58 449 278 0 0
T93 1108 936 0 0
T95 544 370 0 0
T96 377 205 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 121971811 0 0
T4 342881 342388 0 0
T5 294896 294466 0 0
T6 178386 177811 0 0
T17 52694 52309 0 0
T30 69037 68530 0 0
T31 43673 43325 0 0
T58 27829 27345 0 0
T93 114897 113841 0 0
T95 31068 30701 0 0
T96 24130 23342 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc
Line No.TotalCoveredPercent
TOTAL221045.45
CONT_ASSIGN65100.00
ALWAYS716466.67
CONT_ASSIGN85100.00
CONT_ASSIGN109100.00
ALWAYS1159555.56
CONT_ASSIGN15011100.00
CONT_ASSIGN155100.00
CONT_ASSIGN156100.00
CONT_ASSIGN200100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 0 1
71 1 1
72 1 1
73 1 1
74 0 1
75 1 1
76 0 1
MISSING_ELSE
85 0 1
109 0 1
115 1 1
116 1 1
117 1 1
118 1 1
123 0 1
124 0 1
125 1 1
134 0 1
135 0 1
MISSING_ELSE
150 1 1
155 0 1
156 0 1
200 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc
TotalCoveredPercent
Conditions11436.36
Logical11436.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc
Line No.TotalCoveredPercent
Branches 8 4 50.00
IF 71 4 2 50.00
IF 115 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 122639056 0 0 0
DstReqKnown_A 1562074 1370371 0 0
SrcAckBusyChk_A 122639056 0 0 0
SrcBusyKnown_A 122639056 121971811 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1562074 1370371 0 0
T4 3088 2916 0 0
T5 2718 2544 0 0
T6 1878 1705 0 0
T17 924 749 0 0
T30 806 632 0 0
T31 688 516 0 0
T58 449 278 0 0
T93 1108 936 0 0
T95 544 370 0 0
T96 377 205 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 121971811 0 0
T4 342881 342388 0 0
T5 294896 294466 0 0
T6 178386 177811 0 0
T17 52694 52309 0 0
T30 69037 68530 0 0
T31 43673 43325 0 0
T58 27829 27345 0 0
T93 114897 113841 0 0
T95 31068 30701 0 0
T96 24130 23342 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc
Line No.TotalCoveredPercent
TOTAL221045.45
CONT_ASSIGN65100.00
ALWAYS716466.67
CONT_ASSIGN85100.00
CONT_ASSIGN109100.00
ALWAYS1159555.56
CONT_ASSIGN15011100.00
CONT_ASSIGN155100.00
CONT_ASSIGN156100.00
CONT_ASSIGN200100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 0 1
71 1 1
72 1 1
73 1 1
74 0 1
75 1 1
76 0 1
MISSING_ELSE
85 0 1
109 0 1
115 1 1
116 1 1
117 1 1
118 1 1
123 0 1
124 0 1
125 1 1
134 0 1
135 0 1
MISSING_ELSE
150 1 1
155 0 1
156 0 1
200 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc
TotalCoveredPercent
Conditions11436.36
Logical11436.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc
Line No.TotalCoveredPercent
Branches 8 4 50.00
IF 71 4 2 50.00
IF 115 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 122639056 0 0 0
DstReqKnown_A 1562074 1370371 0 0
SrcAckBusyChk_A 122639056 0 0 0
SrcBusyKnown_A 122639056 121971811 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1562074 1370371 0 0
T4 3088 2916 0 0
T5 2718 2544 0 0
T6 1878 1705 0 0
T17 924 749 0 0
T30 806 632 0 0
T31 688 516 0 0
T58 449 278 0 0
T93 1108 936 0 0
T95 544 370 0 0
T96 377 205 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 121971811 0 0
T4 342881 342388 0 0
T5 294896 294466 0 0
T6 178386 177811 0 0
T17 52694 52309 0 0
T30 69037 68530 0 0
T31 43673 43325 0 0
T58 27829 27345 0 0
T93 114897 113841 0 0
T95 31068 30701 0 0
T96 24130 23342 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc
Line No.TotalCoveredPercent
TOTAL221045.45
CONT_ASSIGN65100.00
ALWAYS716466.67
CONT_ASSIGN85100.00
CONT_ASSIGN109100.00
ALWAYS1159555.56
CONT_ASSIGN15011100.00
CONT_ASSIGN155100.00
CONT_ASSIGN156100.00
CONT_ASSIGN200100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 0 1
71 1 1
72 1 1
73 1 1
74 0 1
75 1 1
76 0 1
MISSING_ELSE
85 0 1
109 0 1
115 1 1
116 1 1
117 1 1
118 1 1
123 0 1
124 0 1
125 1 1
134 0 1
135 0 1
MISSING_ELSE
150 1 1
155 0 1
156 0 1
200 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc
TotalCoveredPercent
Conditions11436.36
Logical11436.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc
Line No.TotalCoveredPercent
Branches 8 4 50.00
IF 71 4 2 50.00
IF 115 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 122639056 0 0 0
DstReqKnown_A 1562074 1370371 0 0
SrcAckBusyChk_A 122639056 0 0 0
SrcBusyKnown_A 122639056 121971811 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1562074 1370371 0 0
T4 3088 2916 0 0
T5 2718 2544 0 0
T6 1878 1705 0 0
T17 924 749 0 0
T30 806 632 0 0
T31 688 516 0 0
T58 449 278 0 0
T93 1108 936 0 0
T95 544 370 0 0
T96 377 205 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 121971811 0 0
T4 342881 342388 0 0
T5 294896 294466 0 0
T6 178386 177811 0 0
T17 52694 52309 0 0
T30 69037 68530 0 0
T31 43673 43325 0 0
T58 27829 27345 0 0
T93 114897 113841 0 0
T95 31068 30701 0 0
T96 24130 23342 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc
Line No.TotalCoveredPercent
TOTAL221045.45
CONT_ASSIGN65100.00
ALWAYS716466.67
CONT_ASSIGN85100.00
CONT_ASSIGN109100.00
ALWAYS1159555.56
CONT_ASSIGN15011100.00
CONT_ASSIGN155100.00
CONT_ASSIGN156100.00
CONT_ASSIGN200100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 0 1
71 1 1
72 1 1
73 1 1
74 0 1
75 1 1
76 0 1
MISSING_ELSE
85 0 1
109 0 1
115 1 1
116 1 1
117 1 1
118 1 1
123 0 1
124 0 1
125 1 1
134 0 1
135 0 1
MISSING_ELSE
150 1 1
155 0 1
156 0 1
200 0 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc
TotalCoveredPercent
Conditions11436.36
Logical11436.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc
Line No.TotalCoveredPercent
Branches 8 4 50.00
IF 71 4 2 50.00
IF 115 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 122639056 0 0 0
DstReqKnown_A 1562074 1370371 0 0
SrcAckBusyChk_A 122639056 0 0 0
SrcBusyKnown_A 122639056 121971811 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1562074 1370371 0 0
T4 3088 2916 0 0
T5 2718 2544 0 0
T6 1878 1705 0 0
T17 924 749 0 0
T30 806 632 0 0
T31 688 516 0 0
T58 449 278 0 0
T93 1108 936 0 0
T95 544 370 0 0
T96 377 205 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 121971811 0 0
T4 342881 342388 0 0
T5 294896 294466 0 0
T6 178386 177811 0 0
T17 52694 52309 0 0
T30 69037 68530 0 0
T31 43673 43325 0 0
T58 27829 27345 0 0
T93 114897 113841 0 0
T95 31068 30701 0 0
T96 24130 23342 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT1,T2,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT1,T2,T3
10CoveredT1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T7
0 0 1 Covered T1,T2,T7
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 122639056 9069 0 0
DstReqKnown_A 1562074 1370371 0 0
SrcAckBusyChk_A 122639056 21 0 0
SrcBusyKnown_A 122639056 121971811 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 9069 0 0
T1 158161 604 0 0
T2 0 663 0 0
T7 0 751 0 0
T11 0 1348 0 0
T12 0 333 0 0
T13 0 332 0 0
T14 0 1594 0 0
T15 0 1719 0 0
T28 38099 0 0 0
T33 277108 0 0 0
T71 11536 0 0 0
T86 54712 0 0 0
T99 97185 0 0 0
T141 0 935 0 0
T142 0 790 0 0
T143 41971 0 0 0
T144 29812 0 0 0
T145 37083 0 0 0
T146 42731 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1562074 1370371 0 0
T4 3088 2916 0 0
T5 2718 2544 0 0
T6 1878 1705 0 0
T17 924 749 0 0
T30 806 632 0 0
T31 688 516 0 0
T58 449 278 0 0
T93 1108 936 0 0
T95 544 370 0 0
T96 377 205 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 21 0 0
T1 158161 2 0 0
T2 0 2 0 0
T7 0 2 0 0
T11 0 4 0 0
T14 0 3 0 0
T15 0 4 0 0
T28 38099 0 0 0
T33 277108 0 0 0
T71 11536 0 0 0
T86 54712 0 0 0
T99 97185 0 0 0
T141 0 2 0 0
T142 0 2 0 0
T143 41971 0 0 0
T144 29812 0 0 0
T145 37083 0 0 0
T146 42731 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122639056 121971811 0 0
T4 342881 342388 0 0
T5 294896 294466 0 0
T6 178386 177811 0 0
T17 52694 52309 0 0
T30 69037 68530 0 0
T31 43673 43325 0 0
T58 27829 27345 0 0
T93 114897 113841 0 0
T95 31068 30701 0 0
T96 24130 23342 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%