Unified Coverage Report :: Module :: chip_earlgrey_asic

Module : chip_earlgrey_asic

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.90	80.00	100.00	95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.83	80.00	100.00	98.48

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.83	80.00	100.00	98.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.77	91.02	80.63	89.66		92.13	80.42

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
top_earlgrey	85.79	90.84	79.08	89.55		91.81	77.66
u_ast	87.36			87.36
u_padring	97.80	99.21	99.81	96.57		99.60	93.81
u_prim_usb_diff_rx	96.30	100.00	88.89			100.00

Line Coverage for Module : chip_earlgrey_asic

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	789	1	0	0.00
CONT_ASSIGN	800	1	0	0.00
CONT_ASSIGN	825	1	0	0.00
CONT_ASSIGN	832	1	0	0.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	842	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	854	1	0	0.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1024	1	1	100.00
CONT_ASSIGN	1025	1	1	100.00
CONT_ASSIGN	1032	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
CONT_ASSIGN	1050	1	1	100.00
CONT_ASSIGN	1051	1	1	100.00
CONT_ASSIGN	1052	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00
CONT_ASSIGN	1057	1	1	100.00
CONT_ASSIGN	1058	1	1	100.00
CONT_ASSIGN	1059	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
214	1	1
215	1	1
789	0	1
800	0	1
825	0	1
832	0	1
839	1	1
842	1	1
848	1	1
850	1	1
854	0	1
857	1	1
1022	1	1
1023	1	1
1024	1	1
1025	1	1
1032	1	1
1049	1	1
1050	1	1
1051	1	1
1052	1	1
1056	1	1
1057	1	1
1058	1	1
1059	1	1

---

Cond Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T45,T1

---

Toggle Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Totals	70	64	91.43
Total Bits	140	134	95.71
Total Bits 0->1	70	70	100.00
Total Bits 1->0	70	64	91.43

Ports	70	64	91.43
Port Bits	140	134	95.71
Port Bits 0->1	70	70	100.00
Port Bits 1->0	70	64	91.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
POR_N	Yes	Yes	T33,T34,T35	Yes	T4,T5,T6	INOUT
USB_P	Yes	Yes	T125,T130,T126	Yes	T125,T126,T48	INOUT
USB_N	Yes	Yes	T125,T126,T48	Yes	T125,T126,T48	INOUT
CC1	No	No		Yes	T36,T37,T38	INOUT
CC2	No	No		Yes	T36,T37,T38	INOUT
FLASH_TEST_VOLT	No	No		Yes	T36,T37,T38	INOUT
FLASH_TEST_MODE0	No	No		Yes	T36,T37,T38	INOUT
FLASH_TEST_MODE1	No	No		Yes	T36,T37,T38	INOUT
OTP_EXT_VOLT	No	No		Yes	T36,T37,T38	INOUT
SPI_HOST_D0	Yes	Yes	T39,T40,T41	Yes	T3,T39,T40	INOUT
SPI_HOST_D1	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INOUT
SPI_HOST_D2	Yes	Yes	T41,T90,T91	Yes	T10,T41,T90	INOUT
SPI_HOST_D3	Yes	Yes	T41,T90,T91	Yes	T41,T90,T91	INOUT
SPI_HOST_CLK	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INOUT
SPI_HOST_CS_L	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INOUT
SPI_DEV_D0	Yes	Yes	T23,T39,T40	Yes	T23,T39,T40	INOUT
SPI_DEV_D1	Yes	Yes	T23,T39,T40	Yes	T23,T39,T40	INOUT
SPI_DEV_D2	Yes	Yes	T41,T90,T91	Yes	T41,T90,T91	INOUT
SPI_DEV_D3	Yes	Yes	T41,T90,T91	Yes	T41,T90,T36	INOUT
SPI_DEV_CLK	Yes	Yes	T23,T39,T40	Yes	T23,T39,T40	INOUT
SPI_DEV_CS_L	Yes	Yes	T23,T3,T39	Yes	T23,T39,T40	INOUT
IOR8	Yes	Yes	T45,T213,T224	Yes	T45,T213,T3	INOUT
IOR9	Yes	Yes	T45,T46,T36	Yes	T45,T213,T3	INOUT
IOA0	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	INOUT
IOA1	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	INOUT
IOA2	Yes	Yes	T51,T52,T167	Yes	T51,T52,T167	INOUT
IOA3	Yes	Yes	T51,T52,T12	Yes	T51,T52,T12	INOUT
IOA4	Yes	Yes	T165,T166,T51	Yes	T165,T166,T51	INOUT
IOA5	Yes	Yes	T165,T166,T51	Yes	T165,T166,T51	INOUT
IOA6	Yes	Yes	T51,T52,T12	Yes	T51,T52,T12	INOUT
IOA7	Yes	Yes	T206,T51,T207	Yes	T206,T51,T207	INOUT
IOA8	Yes	Yes	T206,T51,T207	Yes	T206,T51,T207	INOUT
IOB0	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INOUT
IOB1	Yes	Yes	T55,T56,T57	Yes	T37,T55,T56	INOUT
IOB2	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INOUT
IOB3	Yes	Yes	T45,T213,T224	Yes	T45,T213,T224	INOUT
IOB4	Yes	Yes	T269,T316,T317	Yes	T269,T316,T317	INOUT
IOB5	Yes	Yes	T269,T316,T317	Yes	T269,T316,T317	INOUT
IOB6	Yes	Yes	T45,T213,T51	Yes	T45,T213,T51	INOUT
IOB7	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INOUT
IOB8	Yes	Yes	T45,T213,T51	Yes	T213,T51,T224	INOUT
IOB9	Yes	Yes	T30,T45,T51	Yes	T30,T51,T52	INOUT
IOB10	Yes	Yes	T30,T51,T52	Yes	T30,T51,T52	INOUT
IOB11	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	INOUT
IOB12	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	INOUT
IOC0	Yes	Yes	T4,T5,T33	Yes	T23,T275,T320	INOUT
IOC1	Yes	Yes	T23,T319,T320	Yes	T23,T320,T373	INOUT
IOC2	Yes	Yes	T23,T319,T320	Yes	T23,T320,T373	INOUT
IOC3	Yes	Yes	T321,T322,T364	Yes	T321,T322,T364	INOUT
IOC4	Yes	Yes	T33,T321,T322	Yes	T33,T321,T322	INOUT
IOC5	Yes	Yes	T23,T123,T124	Yes	T23,T123,T124	INOUT
IOC6	Yes	Yes	T71,T42,T72	Yes	T71,T42,T72	INOUT
IOC7	Yes	Yes	T45,T213,T224	Yes	T45,T213,T224	INOUT
IOC8	Yes	Yes	T123,T124,T121	Yes	T23,T123,T124	INOUT
IOC9	Yes	Yes	T45,T213,T51	Yes	T45,T213,T51	INOUT
IOC10	Yes	Yes	T51,T52,T314	Yes	T51,T52,T314	INOUT
IOC11	Yes	Yes	T51,T52,T314	Yes	T51,T52,T314	INOUT
IOC12	Yes	Yes	T51,T52,T314	Yes	T51,T52,T314	INOUT
IOR0	Yes	Yes	T71,T22,T23	Yes	T71,T22,T23	INOUT
IOR1	Yes	Yes	T71,T22,T23	Yes	T71,T22,T23	INOUT
IOR2	Yes	Yes	T71,T22,T23	Yes	T71,T22,T23	INOUT
IOR3	Yes	Yes	T71,T22,T23	Yes	T71,T22,T23	INOUT
IOR4	Yes	Yes	T22,T23,T70	Yes	T71,T22,T72	INOUT
IOR5	Yes	Yes	T51,T52,T46	Yes	T51,T52,T46	INOUT
IOR6	Yes	Yes	T51,T52,T129	Yes	T51,T52,T46	INOUT
IOR7	Yes	Yes	T51,T52,T129	Yes	T51,T52,T129	INOUT
IOR10	Yes	Yes	T51,T52,T129	Yes	T51,T52,T129	INOUT
IOR11	Yes	Yes	T51,T52,T129	Yes	T51,T52,T129	INOUT
IOR12	Yes	Yes	T51,T52,T129	Yes	T51,T52,T129	INOUT
IOR13	Yes	Yes	T1,T213,T2	Yes	T1,T213,T2	INOUT

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	789	1	0	0.00
CONT_ASSIGN	800	1	0	0.00
CONT_ASSIGN	825	1	0	0.00
CONT_ASSIGN	832	1	0	0.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	842	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	854	1	0	0.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	1022	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1024	1	1	100.00
CONT_ASSIGN	1025	1	1	100.00
CONT_ASSIGN	1032	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
CONT_ASSIGN	1050	1	1	100.00
CONT_ASSIGN	1051	1	1	100.00
CONT_ASSIGN	1052	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00
CONT_ASSIGN	1057	1	1	100.00
CONT_ASSIGN	1058	1	1	100.00
CONT_ASSIGN	1059	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
214	1	1
215	1	1
789	0	1
800	0	1
825	0	1
832	0	1
839	1	1
842	1	1
848	1	1
850	1	1
854	0	1
857	1	1
1022	1	1
1023	1	1
1024	1	1
1025	1	1
1032	1	1
1049	1	1
1050	1	1
1051	1	1
1052	1	1
1056	1	1
1057	1	1
1058	1	1
1059	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T45,T1

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	66	64	96.97
Total Bits	132	130	98.48
Total Bits 0->1	66	66	100.00
Total Bits 1->0	66	64	96.97

Ports	66	64	96.97
Port Bits	132	130	98.48
Port Bits 0->1	66	66	100.00
Port Bits 1->0	66	64	96.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
POR_N	Yes	Yes	T33,T34,T35	Yes	T4,T5,T6	INOUT
USB_P	Yes	Yes	T125,T130,T126	Yes	T125,T126,T48	INOUT
USB_N	Yes	Yes	T125,T126,T48	Yes	T125,T126,T48	INOUT
CC1	No	No		Yes	T36,T37,T38	INOUT
CC2	No	No		Yes	T36,T37,T38	INOUT
FLASH_TEST_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0	Yes	Yes	T39,T40,T41	Yes	T3,T39,T40	INOUT
SPI_HOST_D1	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INOUT
SPI_HOST_D2	Yes	Yes	T41,T90,T91	Yes	T10,T41,T90	INOUT
SPI_HOST_D3	Yes	Yes	T41,T90,T91	Yes	T41,T90,T91	INOUT
SPI_HOST_CLK	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INOUT
SPI_HOST_CS_L	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INOUT
SPI_DEV_D0	Yes	Yes	T23,T39,T40	Yes	T23,T39,T40	INOUT
SPI_DEV_D1	Yes	Yes	T23,T39,T40	Yes	T23,T39,T40	INOUT
SPI_DEV_D2	Yes	Yes	T41,T90,T91	Yes	T41,T90,T91	INOUT
SPI_DEV_D3	Yes	Yes	T41,T90,T91	Yes	T41,T90,T36	INOUT
SPI_DEV_CLK	Yes	Yes	T23,T39,T40	Yes	T23,T39,T40	INOUT
SPI_DEV_CS_L	Yes	Yes	T23,T3,T39	Yes	T23,T39,T40	INOUT
IOR8	Yes	Yes	T45,T213,T224	Yes	T45,T213,T3	INOUT
IOR9	Yes	Yes	T45,T46,T36	Yes	T45,T213,T3	INOUT
IOA0	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	INOUT
IOA1	Yes	Yes	T32,T42,T43	Yes	T32,T42,T43	INOUT
IOA2	Yes	Yes	T51,T52,T167	Yes	T51,T52,T167	INOUT
IOA3	Yes	Yes	T51,T52,T12	Yes	T51,T52,T12	INOUT
IOA4	Yes	Yes	T165,T166,T51	Yes	T165,T166,T51	INOUT
IOA5	Yes	Yes	T165,T166,T51	Yes	T165,T166,T51	INOUT
IOA6	Yes	Yes	T51,T52,T12	Yes	T51,T52,T12	INOUT
IOA7	Yes	Yes	T206,T51,T207	Yes	T206,T51,T207	INOUT
IOA8	Yes	Yes	T206,T51,T207	Yes	T206,T51,T207	INOUT
IOB0	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INOUT
IOB1	Yes	Yes	T55,T56,T57	Yes	T37,T55,T56	INOUT
IOB2	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INOUT
IOB3	Yes	Yes	T45,T213,T224	Yes	T45,T213,T224	INOUT
IOB4	Yes	Yes	T269,T316,T317	Yes	T269,T316,T317	INOUT
IOB5	Yes	Yes	T269,T316,T317	Yes	T269,T316,T317	INOUT
IOB6	Yes	Yes	T45,T213,T51	Yes	T45,T213,T51	INOUT
IOB7	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INOUT
IOB8	Yes	Yes	T45,T213,T51	Yes	T213,T51,T224	INOUT
IOB9	Yes	Yes	T30,T45,T51	Yes	T30,T51,T52	INOUT
IOB10	Yes	Yes	T30,T51,T52	Yes	T30,T51,T52	INOUT
IOB11	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	INOUT
IOB12	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	INOUT
IOC0	Yes	Yes	T4,T5,T33	Yes	T23,T275,T320	INOUT
IOC1	Yes	Yes	T23,T319,T320	Yes	T23,T320,T373	INOUT
IOC2	Yes	Yes	T23,T319,T320	Yes	T23,T320,T373	INOUT
IOC3	Yes	Yes	T321,T322,T364	Yes	T321,T322,T364	INOUT
IOC4	Yes	Yes	T33,T321,T322	Yes	T33,T321,T322	INOUT
IOC5	Yes	Yes	T23,T123,T124	Yes	T23,T123,T124	INOUT
IOC6	Yes	Yes	T71,T42,T72	Yes	T71,T42,T72	INOUT
IOC7	Yes	Yes	T45,T213,T224	Yes	T45,T213,T224	INOUT
IOC8	Yes	Yes	T123,T124,T121	Yes	T23,T123,T124	INOUT
IOC9	Yes	Yes	T45,T213,T51	Yes	T45,T213,T51	INOUT
IOC10	Yes	Yes	T51,T52,T314	Yes	T51,T52,T314	INOUT
IOC11	Yes	Yes	T51,T52,T314	Yes	T51,T52,T314	INOUT
IOC12	Yes	Yes	T51,T52,T314	Yes	T51,T52,T314	INOUT
IOR0	Yes	Yes	T71,T22,T23	Yes	T71,T22,T23	INOUT
IOR1	Yes	Yes	T71,T22,T23	Yes	T71,T22,T23	INOUT
IOR2	Yes	Yes	T71,T22,T23	Yes	T71,T22,T23	INOUT
IOR3	Yes	Yes	T71,T22,T23	Yes	T71,T22,T23	INOUT
IOR4	Yes	Yes	T22,T23,T70	Yes	T71,T22,T72	INOUT
IOR5	Yes	Yes	T51,T52,T46	Yes	T51,T52,T46	INOUT
IOR6	Yes	Yes	T51,T52,T129	Yes	T51,T52,T46	INOUT
IOR7	Yes	Yes	T51,T52,T129	Yes	T51,T52,T129	INOUT
IOR10	Yes	Yes	T51,T52,T129	Yes	T51,T52,T129	INOUT
IOR11	Yes	Yes	T51,T52,T129	Yes	T51,T52,T129	INOUT
IOR12	Yes	Yes	T51,T52,T129	Yes	T51,T52,T129	INOUT
IOR13	Yes	Yes	T1,T213,T2	Yes	T1,T213,T2	INOUT