Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3790634	1			T75	361		T76	2139		T77	1211
values[2]	740644	1			T76	204		T77	350		T272	39
values[3]	96204	1			T77	15		T271	12		T469	419
values[4]	50417	1			T271	12		T469	268		T773	1
values[5]	35361	1			T271	12		T469	149		T773	1
values[6]	27309	1			T271	12		T469	65		T773	1
values[7]	22574	1			T271	13		T469	44		T773	1
values[8]	19502	1			T271	12		T469	22		T773	1
values[9]	18272	1			T271	12		T469	25		T773	1
values[10]	16586	1			T271	12		T469	13		T773	1
values[11]	16143	1			T271	12		T469	9		T773	1
values[12]	15306	1			T271	12		T469	12		T773	1
values[13]	14292	1			T271	12		T469	7		T773	1
values[14]	13256	1			T271	12		T469	10		T773	1
values[15]	12919	1			T271	12		T469	6		T773	1
values[16]	12344	1			T271	12		T469	5		T773	1
values[17]	11932	1			T271	12		T469	12		T773	1
values[18]	11662	1			T271	12		T469	21		T773	1
values[19]	11254	1			T271	12		T469	9		T773	1
values[20]	10801	1			T271	12		T469	16		T773	1
values[21]	10744	1			T271	12		T469	13		T773	1
values[22]	10387	1			T271	12		T469	9		T773	1
values[23]	9982	1			T271	12		T469	11		T773	1
values[24]	9814	1			T271	12		T469	15		T773	1
values[25]	9371	1			T271	12		T469	16		T773	1
values[26]	8925	1			T271	13		T469	7		T773	1
values[27]	8661	1			T271	13		T469	9		T773	1
values[28]	7931	1			T271	12		T469	9		T773	1
values[29]	7537	1			T271	12		T469	6		T773	1
values[30]	7035	1			T271	12		T469	8		T773	1
values[31]	6419	1			T271	12		T469	6		T773	1
values[32]	6016	1			T271	13		T469	10		T773	1
values[33]	5472	1			T271	12		T469	14		T773	1
values[34]	5115	1			T271	12		T469	11		T773	1
values[35]	4814	1			T271	12		T469	10		T773	1
values[36]	4457	1			T271	13		T469	7		T773	1
values[37]	4250	1			T271	12		T469	12		T773	1
values[38]	4028	1			T271	12		T469	8		T773	1
values[39]	3883	1			T271	13		T469	10		T773	1
values[40]	3813	1			T271	12		T469	17		T773	1
values[41]	3708	1			T271	12		T469	15		T773	1
values[42]	3487	1			T271	12		T469	10		T773	1
values[43]	3429	1			T271	12		T469	11		T773	1
values[44]	3362	1			T271	12		T469	6		T773	1
values[45]	3366	1			T271	12		T469	9		T773	1
values[46]	3240	1			T271	13		T469	10		T773	1
values[47]	3161	1			T271	13		T469	8		T773	1
values[48]	3100	1			T271	12		T469	6		T773	1
values[49]	3084	1			T271	13		T469	7		T773	1
values[50]	2940	1			T271	13		T469	9		T773	1
values[51]	2992	1			T271	12		T469	12		T773	1
values[52]	2869	1			T271	12		T469	16		T773	1
values[53]	2827	1			T271	12		T469	13		T773	1
values[54]	2718	1			T271	12		T469	11		T773	1
values[55]	2748	1			T271	12		T469	11		T773	1
values[56]	2684	1			T271	12		T469	8		T773	1
values[57]	2546	1			T271	12		T469	16		T773	1
values[58]	2437	1			T271	12		T469	8		T773	1
values[59]	2382	1			T271	12		T469	7		T773	1
values[60]	2434	1			T271	12		T469	9		T773	1
values[61]	2696	1			T271	12		T469	17		T773	1
values[62]	4221	1			T271	14		T469	38		T773	1
values[63]	14964	1			T271	13		T469	114		T773	1
values[64]	227355	1			T271	2081		T469	137		T773	208

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4862965	1			T75	378		T76	2220		T77	1418
values[2]	803675	1			T76	161		T77	294		T272	18
values[3]	73953	1			T76	1		T77	25		T271	189
values[4]	13629	1			T271	63		T469	3		T773	3
values[5]	5480	1			T271	18		T773	1		T557	3
values[6]	3145	1			T271	5		T773	1		T557	4
values[7]	2280	1			T271	2		T557	3		T512	1
values[8]	1951	1			T557	1		T512	1		T445	3
values[9]	1811	1			T557	2		T512	1		T445	2
values[10]	1633	1			T557	1		T445	2		T882	2
values[11]	1517	1			T557	2		T445	2		T882	3
values[12]	1405	1			T557	2		T445	1		T882	2
values[13]	1266	1			T557	1		T445	2		T882	1
values[14]	1265	1			T557	2		T445	1		T882	1
values[15]	1133	1			T557	1		T445	3		T882	2
values[16]	1038	1			T557	2		T445	4		T882	2
values[17]	1099	1			T557	1		T445	5		T882	4
values[18]	1045	1			T557	1		T445	1		T882	4
values[19]	974	1			T557	1		T445	2		T882	1
values[20]	922	1			T557	5		T445	2		T882	3
values[21]	921	1			T557	4		T445	1		T882	3
values[22]	887	1			T557	1		T445	4		T882	1
values[23]	838	1			T557	2		T445	1		T882	4
values[24]	780	1			T557	1		T445	1		T882	3
values[25]	791	1			T557	1		T445	1		T882	1
values[26]	747	1			T557	6		T445	1		T882	3
values[27]	640	1			T557	1		T445	1		T882	1
values[28]	583	1			T557	3		T445	2		T882	2
values[29]	576	1			T557	6		T445	1		T882	1
values[30]	568	1			T557	2		T445	2		T882	2
values[31]	584	1			T557	7		T445	3		T882	1
values[32]	585	1			T557	2		T445	1		T882	10
values[33]	573	1			T557	1		T445	1		T882	2
values[34]	564	1			T557	2		T445	2		T882	2
values[35]	509	1			T557	2		T445	1		T882	1
values[36]	506	1			T557	1		T445	2		T882	2
values[37]	526	1			T557	1		T445	1		T882	2
values[38]	511	1			T557	1		T445	1		T882	1
values[39]	471	1			T557	1		T445	2		T882	2
values[40]	492	1			T557	1		T445	1		T882	2
values[41]	438	1			T557	1		T445	3		T882	3
values[42]	449	1			T557	1		T445	2		T882	2
values[43]	452	1			T557	1		T445	1		T882	2
values[44]	410	1			T557	1		T445	1		T882	1
values[45]	416	1			T557	1		T445	3		T882	2
values[46]	411	1			T557	1		T445	4		T882	6
values[47]	432	1			T557	3		T445	2		T882	2
values[48]	399	1			T557	3		T445	1		T882	1
values[49]	372	1			T557	1		T445	1		T882	1
values[50]	398	1			T557	3		T445	2		T882	1
values[51]	426	1			T557	1		T445	8		T882	2
values[52]	392	1			T557	2		T445	3		T882	2
values[53]	364	1			T557	1		T445	2		T882	1
values[54]	379	1			T557	1		T445	6		T882	1
values[55]	366	1			T557	1		T445	3		T882	1
values[56]	379	1			T557	4		T445	1		T882	3
values[57]	351	1			T557	1		T445	1		T882	1
values[58]	344	1			T557	3		T445	1		T882	1
values[59]	358	1			T557	1		T445	1		T882	2
values[60]	385	1			T557	3		T445	1		T882	1
values[61]	433	1			T557	5		T445	2		T882	2
values[62]	689	1			T557	1		T445	1		T882	1
values[63]	3167	1			T557	10		T445	6		T882	11
values[64]	26529	1			T557	104		T445	129		T882	133

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	637811	1			T75	428		T76	21		T77	44
values[2]	2693720	1			T76	2235		T77	1133		T272	435
values[3]	1144074	1			T76	180		T77	492		T272	36
values[4]	132991	1			T77	18		T271	13		T469	470
values[5]	69030	1			T271	12		T469	275		T773	1
values[6]	46412	1			T271	12		T469	159		T773	1
values[7]	34719	1			T271	12		T469	63		T773	1
values[8]	27776	1			T271	12		T469	37		T773	1
values[9]	23861	1			T271	12		T469	16		T773	1
values[10]	21236	1			T271	12		T469	13		T773	1
values[11]	19044	1			T271	12		T469	12		T773	1
values[12]	17609	1			T271	12		T469	16		T773	1
values[13]	16591	1			T271	12		T469	12		T773	1
values[14]	16155	1			T271	12		T469	20		T773	1
values[15]	15254	1			T271	13		T469	18		T773	1
values[16]	14483	1			T271	12		T469	16		T773	1
values[17]	13872	1			T271	12		T469	19		T773	1
values[18]	13838	1			T271	13		T469	13		T773	1
values[19]	13120	1			T271	12		T469	7		T773	1
values[20]	12855	1			T271	12		T469	11		T773	1
values[21]	12269	1			T271	12		T469	7		T773	1
values[22]	11902	1			T271	12		T469	14		T773	1
values[23]	11706	1			T271	12		T469	8		T773	1
values[24]	11178	1			T271	12		T469	8		T773	1
values[25]	10895	1			T271	12		T469	8		T773	1
values[26]	10181	1			T271	12		T469	6		T773	1
values[27]	9604	1			T271	12		T469	6		T773	1
values[28]	8917	1			T271	12		T469	7		T773	1
values[29]	8385	1			T271	12		T469	13		T773	1
values[30]	7891	1			T271	12		T469	15		T773	1
values[31]	7543	1			T271	12		T469	13		T773	1
values[32]	6890	1			T271	14		T469	19		T773	1
values[33]	6142	1			T271	12		T469	19		T773	1
values[34]	5707	1			T271	12		T469	18		T773	1
values[35]	5315	1			T271	12		T469	7		T773	1
values[36]	4982	1			T271	12		T469	9		T773	1
values[37]	4640	1			T271	12		T469	9		T773	1
values[38]	4293	1			T271	12		T469	18		T773	1
values[39]	4087	1			T271	12		T469	13		T773	1
values[40]	3966	1			T271	12		T469	14		T773	1
values[41]	3729	1			T271	13		T469	8		T773	1
values[42]	3740	1			T271	13		T469	10		T773	1
values[43]	3767	1			T271	13		T469	13		T773	1
values[44]	3531	1			T271	12		T469	15		T773	1
values[45]	3421	1			T271	12		T469	11		T773	1
values[46]	3273	1			T271	12		T469	10		T773	1
values[47]	3338	1			T271	12		T469	9		T773	1
values[48]	3209	1			T271	12		T469	12		T773	1
values[49]	3160	1			T271	12		T469	7		T773	1
values[50]	3099	1			T271	12		T469	9		T773	1
values[51]	3029	1			T271	12		T469	13		T773	1
values[52]	3054	1			T271	12		T469	7		T773	1
values[53]	2967	1			T271	12		T469	6		T773	1
values[54]	2977	1			T271	13		T469	11		T773	1
values[55]	2967	1			T271	12		T469	7		T773	1
values[56]	2876	1			T271	12		T469	10		T773	1
values[57]	2803	1			T271	12		T469	8		T773	1
values[58]	2741	1			T271	12		T469	11		T773	2
values[59]	2640	1			T271	12		T469	4		T773	1
values[60]	2621	1			T271	12		T469	6		T773	1
values[61]	2862	1			T271	12		T469	7		T773	1
values[62]	4147	1			T271	13		T469	39		T773	1
values[63]	19656	1			T271	180		T469	80		T773	6
values[64]	218518	1			T271	1917		T469	91		T773	140