Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2315739	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34891145

1

T4

32796

T5

14777

T6

25927

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25753994	1			T4	22990		T5	6483		T6	13289
values[0x0]	9636161	1			T4	9806		T5	8294		T6	12638
values[0x1]	1816729	1			T4	73		T5	1129		T6	940

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	634108	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36572776

1

T4

32869

T5

15906

T6

26867

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17417555	1			T4	16435		T5	7954		T6	13434
valid_sources[0x01]	17415721	1			T4	16434		T5	7952		T6	13433
valid_sources[0x02]	38320	1			T148	702		T149	93		T150	333
valid_sources[0x03]	38099	1			T81	4		T148	837		T149	77
valid_sources[0x04]	37376	1			T199	1		T9	1		T148	799
valid_sources[0x05]	38059	1			T79	9		T148	920		T149	71
valid_sources[0x06]	40884	1			T199	1		T148	813		T149	82
valid_sources[0x07]	37086	1			T79	4		T9	2		T148	817
valid_sources[0x08]	38905	1			T199	1		T148	810		T149	78
valid_sources[0x09]	37024	1			T148	856		T149	88		T150	396
valid_sources[0x0a]	37342	1			T79	3		T9	1		T148	773
valid_sources[0x0b]	37266	1			T81	2		T198	8		T9	2
valid_sources[0x0c]	38875	1			T148	817		T149	67		T150	501
valid_sources[0x0d]	38296	1			T199	1		T9	1		T148	770
valid_sources[0x0e]	38123	1			T9	3		T148	892		T149	93
valid_sources[0x0f]	37502	1			T79	1		T199	2		T9	1
valid_sources[0x10]	38034	1			T148	783		T149	87		T150	279
valid_sources[0x11]	38086	1			T199	1		T148	879		T149	87
valid_sources[0x12]	38055	1			T81	3		T199	1		T9	1
valid_sources[0x13]	38363	1			T199	1		T9	2		T148	750
valid_sources[0x14]	37553	1			T148	740		T149	99		T150	483
valid_sources[0x15]	38369	1			T148	860		T149	94		T150	389
valid_sources[0x16]	39128	1			T199	2		T148	836		T149	88
valid_sources[0x17]	40192	1			T79	1		T199	1		T9	1
valid_sources[0x18]	37815	1			T199	1		T148	979		T149	92
valid_sources[0x19]	37866	1			T79	1		T199	1		T9	2
valid_sources[0x1a]	40630	1			T81	1		T148	893		T149	95
valid_sources[0x1b]	38533	1			T81	1		T9	1		T148	790
valid_sources[0x1c]	37971	1			T9	1		T148	901		T149	104
valid_sources[0x1d]	38899	1			T198	8		T199	2		T9	1
valid_sources[0x1e]	37724	1			T80	39		T9	1		T148	804
valid_sources[0x1f]	37921	1			T79	3		T81	2		T9	1
valid_sources[0x20]	37864	1			T198	2		T199	1		T148	907

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25036724

1

T4

22990

T5

6483

T6

13289

values[0x0]

all_enables

biggest_size

9599044

1

T4

9806

T5

8294

T6

12638

values[0x1]

all_enables

biggest_size

255377

1

T79

21

T80

18

T81

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2937055	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

465714

1

T75

51

T76

300

T77

221

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1152044	1			T75	122		T76	742		T77	522
values[0x0]	1099183	1			T75	133		T76	750		T77	535
values[0x1]	1151542	1			T75	106		T76	851		T77	519

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2273915	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1128854

1

T75

107

T76

777

T77

514

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54032	1			T76	40		T77	17		T208	5
valid_sources[0x01]	52613	1			T75	9		T76	40		T77	20
valid_sources[0x02]	53097	1			T75	8		T76	34		T77	9
valid_sources[0x03]	53003	1			T75	34		T76	25		T77	44
valid_sources[0x04]	52832	1			T76	21		T77	20		T208	12
valid_sources[0x05]	53560	1			T75	19		T76	30		T77	39
valid_sources[0x06]	53702	1			T76	34		T77	24		T272	1
valid_sources[0x07]	54417	1			T76	34		T77	14		T208	54
valid_sources[0x08]	53268	1			T75	5		T76	37		T77	21
valid_sources[0x09]	52978	1			T76	37		T77	28		T271	34
valid_sources[0x0a]	53027	1			T75	7		T76	57		T77	14
valid_sources[0x0b]	52690	1			T75	10		T76	31		T77	28
valid_sources[0x0c]	52790	1			T76	41		T77	46		T208	10
valid_sources[0x0d]	52688	1			T76	24		T77	20		T271	45
valid_sources[0x0e]	53488	1			T76	28		T77	27		T208	5
valid_sources[0x0f]	53920	1			T76	25		T77	21		T271	45
valid_sources[0x10]	53939	1			T75	9		T76	50		T77	27
valid_sources[0x11]	53016	1			T76	23		T77	28		T271	36
valid_sources[0x12]	52998	1			T76	39		T77	15		T208	34
valid_sources[0x13]	53508	1			T75	13		T76	28		T77	21
valid_sources[0x14]	53260	1			T76	48		T77	20		T208	9
valid_sources[0x15]	52800	1			T75	9		T76	21		T77	26
valid_sources[0x16]	53783	1			T76	31		T77	28		T272	1
valid_sources[0x17]	53516	1			T76	25		T77	42		T208	10
valid_sources[0x18]	52102	1			T76	34		T77	22		T271	41
valid_sources[0x19]	52163	1			T75	5		T76	30		T77	22
valid_sources[0x1a]	53333	1			T75	16		T76	34		T77	9
valid_sources[0x1b]	54513	1			T76	52		T77	22		T208	19
valid_sources[0x1c]	54668	1			T75	15		T76	51		T77	29
valid_sources[0x1d]	52797	1			T76	33		T77	20		T271	44
valid_sources[0x1e]	52752	1			T75	23		T76	36		T77	24
valid_sources[0x1f]	53100	1			T76	43		T77	33		T208	14
valid_sources[0x20]	53896	1			T76	44		T77	22		T208	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48527

1

T75

8

T76

26

T77

23

values[0x0]

all_enables

biggest_size

368104

1

T75

40

T76

248

T77

176

values[0x1]

all_enables

biggest_size

49083

1

T75

3

T76

26

T77

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3145178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

513089

1

T75

49

T76

325

T77

269

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1251300	1			T75	126		T76	809		T77	589
values[0x0]	1156650	1			T75	109		T76	742		T77	589
values[0x1]	1250317	1			T75	143		T76	831		T77	559

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2412773	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1245494

1

T75

120

T76

797

T77

621

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57679	1			T77	31		T208	18		T271	60
valid_sources[0x01]	56914	1			T75	5		T76	15		T77	29
valid_sources[0x02]	58769	1			T75	9		T76	60		T77	30
valid_sources[0x03]	57077	1			T75	25		T76	34		T77	29
valid_sources[0x04]	57367	1			T76	28		T77	36		T208	6
valid_sources[0x05]	56552	1			T75	14		T76	14		T77	22
valid_sources[0x06]	57283	1			T76	2		T77	25		T271	54
valid_sources[0x07]	58029	1			T76	122		T77	29		T208	47
valid_sources[0x08]	57729	1			T75	11		T76	37		T77	19
valid_sources[0x09]	57862	1			T76	41		T77	23		T271	32
valid_sources[0x0a]	57237	1			T75	6		T76	29		T77	27
valid_sources[0x0b]	55582	1			T75	17		T76	31		T77	25
valid_sources[0x0c]	56761	1			T76	49		T77	30		T208	20
valid_sources[0x0d]	57775	1			T76	56		T77	23		T271	59
valid_sources[0x0e]	56961	1			T77	21		T208	20		T271	52
valid_sources[0x0f]	57427	1			T76	35		T77	27		T271	59
valid_sources[0x10]	57197	1			T75	9		T76	46		T77	22
valid_sources[0x11]	56396	1			T76	45		T77	25		T271	49
valid_sources[0x12]	57360	1			T76	42		T77	34		T208	28
valid_sources[0x13]	57749	1			T75	7		T76	81		T77	22
valid_sources[0x14]	56038	1			T76	39		T77	25		T208	15
valid_sources[0x15]	57070	1			T75	7		T76	21		T77	33
valid_sources[0x16]	58420	1			T76	144		T77	19		T272	2
valid_sources[0x17]	59026	1			T76	45		T77	27		T208	5
valid_sources[0x18]	57203	1			T76	25		T77	28		T271	42
valid_sources[0x19]	57247	1			T75	17		T76	20		T77	37
valid_sources[0x1a]	56804	1			T75	18		T76	45		T77	28
valid_sources[0x1b]	56802	1			T76	91		T77	30		T208	10
valid_sources[0x1c]	57896	1			T75	13		T76	28		T77	35
valid_sources[0x1d]	57288	1			T76	11		T77	22		T271	65
valid_sources[0x1e]	57958	1			T75	27		T76	18		T77	42
valid_sources[0x1f]	57107	1			T77	37		T208	6		T271	39
valid_sources[0x20]	56107	1			T76	50		T77	26		T208	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53748

1

T75

2

T76

33

T77

27

values[0x0]

all_enables

biggest_size

405527

1

T75

39

T76

252

T77

211

values[0x1]

all_enables

biggest_size

53814

1

T75

8

T76

40

T77

31

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2963796	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

468289

1

T75

58

T76

346

T77

220

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1161894	1			T75	144		T76	831		T77	565
values[0x0]	1109210	1			T75	149		T76	820		T77	524
values[0x1]	1160981	1			T75	135		T76	785		T77	598

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2296337	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1135748

1

T75

148

T76

836

T77

544

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53595	1			T76	33		T77	24		T208	8
valid_sources[0x01]	53945	1			T75	15		T76	54		T77	24
valid_sources[0x02]	54262	1			T75	17		T76	35		T77	22
valid_sources[0x03]	52800	1			T75	24		T76	28		T77	18
valid_sources[0x04]	53279	1			T76	34		T77	27		T208	18
valid_sources[0x05]	53091	1			T75	15		T76	29		T77	24
valid_sources[0x06]	53458	1			T76	45		T77	20		T271	47
valid_sources[0x07]	53950	1			T76	47		T77	23		T208	48
valid_sources[0x08]	54227	1			T75	16		T76	31		T77	14
valid_sources[0x09]	53571	1			T76	21		T77	38		T271	37
valid_sources[0x0a]	53579	1			T75	17		T76	46		T77	30
valid_sources[0x0b]	53564	1			T75	7		T76	32		T77	17
valid_sources[0x0c]	53250	1			T76	21		T77	36		T208	7
valid_sources[0x0d]	53319	1			T76	45		T77	29		T272	1
valid_sources[0x0e]	54004	1			T76	32		T77	30		T208	12
valid_sources[0x0f]	53943	1			T76	56		T77	24		T271	50
valid_sources[0x10]	53345	1			T75	17		T76	44		T77	19
valid_sources[0x11]	53188	1			T76	33		T77	18		T271	52
valid_sources[0x12]	53592	1			T76	26		T77	35		T208	52
valid_sources[0x13]	54581	1			T75	15		T76	54		T77	33
valid_sources[0x14]	53988	1			T76	40		T77	28		T208	5
valid_sources[0x15]	53209	1			T75	10		T76	27		T77	28
valid_sources[0x16]	55385	1			T76	37		T77	24		T272	2
valid_sources[0x17]	53180	1			T76	46		T77	27		T208	18
valid_sources[0x18]	52932	1			T76	32		T77	19		T271	46
valid_sources[0x19]	52598	1			T75	9		T76	39		T77	29
valid_sources[0x1a]	52776	1			T75	11		T76	38		T77	23
valid_sources[0x1b]	54809	1			T76	38		T77	28		T208	9
valid_sources[0x1c]	54628	1			T75	19		T76	39		T77	21
valid_sources[0x1d]	52887	1			T76	26		T77	21		T271	40
valid_sources[0x1e]	54094	1			T75	29		T76	21		T77	26
valid_sources[0x1f]	53458	1			T76	42		T77	29		T208	16
valid_sources[0x20]	53231	1			T76	25		T77	22		T208	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48947

1

T75

4

T76

37

T77

24

values[0x0]

all_enables

biggest_size

370441

1

T75

48

T76

275

T77

170

values[0x1]

all_enables

biggest_size

48901

1

T75

6

T76

34

T77

26