Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	501767176	59734638	0	0
DepthKnown_A	501767176	501660239	0	0
RvalidKnown_A	501767176	501660239	0	0
WreadyKnown_A	501767176	501660239	0	0
gen_passthru_fifo.paramCheckPass	1009	1009	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	59734638	0	0
T4	143373	43477	0	0
T5	245462	30952	0	0
T6	406690	51656	0	0
T17	197999	209060	0	0
T18	205102	16790	0	0
T19	153112	171683	0	0
T42	271588	34343	0	0
T53	204907	219447	0	0
T54	121774	137764	0	0
T86	77188	8496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1009	1009	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	501767176	45018517	0	0
DepthKnown_A	501767176	501660239	0	0
RvalidKnown_A	501767176	501660239	0	0
WreadyKnown_A	501767176	501660239	0	0
gen_passthru_fifo.paramCheckPass	1009	1009	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	45018517	0	0
T4	143373	39549	0	0
T5	245462	22165	0	0
T6	406690	42950	0	0
T17	197999	191245	0	0
T18	205102	13074	0	0
T19	153112	153982	0	0
T42	271588	25477	0	0
T53	204907	200358	0	0
T54	121774	119165	0	0
T86	77188	6174	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1009	1009	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	501767176	41928875	0	0
DepthKnown_A	501767176	501660239	0	0
RvalidKnown_A	501767176	501660239	0	0
WreadyKnown_A	501767176	501660239	0	0
gen_passthru_fifo.paramCheckPass	1009	1009	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	41928875	0	0
T4	143373	33038	0	0
T5	245462	16300	0	0
T6	406690	27656	0	0
T17	197999	263910	0	0
T18	205102	10122	0	0
T19	153112	231372	0	0
T42	271588	18648	0	0
T53	204907	250032	0	0
T54	121774	161213	0	0
T86	77188	3990	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1009	1009	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	501767176	34836788	0	0
DepthKnown_A	501767176	501660239	0	0
RvalidKnown_A	501767176	501660239	0	0
WreadyKnown_A	501767176	501660239	0	0
gen_passthru_fifo.paramCheckPass	1009	1009	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	34836788	0	0
T4	143373	32869	0	0
T5	245462	15906	0	0
T6	406690	26867	0	0
T17	197999	189186	0	0
T18	205102	9866	0	0
T19	153112	151539	0	0
T42	271588	18256	0	0
T53	204907	197793	0	0
T54	121774	111001	0	0
T86	77188	3847	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501767176	501660239	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1009	1009	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584293779	91633	0	0
DepthKnown_A	584293779	584175214	0	0
RvalidKnown_A	584293779	584175214	0	0
WreadyKnown_A	584293779	584175214	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	91633	0	0
T4	143373	29	0	0
T5	245462	153	0	0
T6	406690	435	0	0
T17	197999	49	0	0
T18	205102	34	0	0
T19	153112	49	0	0
T42	271588	151	0	0
T53	204907	56	0	0
T54	121774	34	0	0
T86	77188	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584293779	92945	0	0
DepthKnown_A	584293779	584175214	0	0
RvalidKnown_A	584293779	584175214	0	0
WreadyKnown_A	584293779	584175214	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	92945	0	0
T4	143373	29	0	0
T5	245462	153	0	0
T6	406690	435	0	0
T17	197999	49	0	0
T18	205102	34	0	0
T19	153112	49	0	0
T42	271588	151	0	0
T53	204907	56	0	0
T54	121774	34	0	0
T86	77188	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584293779	50927	0	0
DepthKnown_A	584293779	584175214	0	0
RvalidKnown_A	584293779	584175214	0	0
WreadyKnown_A	584293779	584175214	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	50927	0	0
T4	143373	28	0	0
T5	245462	95	0	0
T6	406690	432	0	0
T17	197999	0	0	0
T18	205102	32	0	0
T19	153112	0	0	0
T42	271588	95	0	0
T53	204907	5	0	0
T54	121774	5	0	0
T86	77188	12	0	0
T156	0	12	0	0
T168	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584293779	50927	0	0
DepthKnown_A	584293779	584175214	0	0
RvalidKnown_A	584293779	584175214	0	0
WreadyKnown_A	584293779	584175214	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	50927	0	0
T4	143373	28	0	0
T5	245462	95	0	0
T6	406690	432	0	0
T17	197999	0	0	0
T18	205102	32	0	0
T19	153112	0	0	0
T42	271588	95	0	0
T53	204907	5	0	0
T54	121774	5	0	0
T86	77188	12	0	0
T156	0	12	0	0
T168	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584293779	40706	0	0
DepthKnown_A	584293779	584175214	0	0
RvalidKnown_A	584293779	584175214	0	0
WreadyKnown_A	584293779	584175214	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	40706	0	0
T4	143373	1	0	0
T5	245462	58	0	0
T6	406690	3	0	0
T17	197999	49	0	0
T18	205102	2	0	0
T19	153112	49	0	0
T42	271588	56	0	0
T53	204907	51	0	0
T54	121774	29	0	0
T86	77188	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584293779	42018	0	0
DepthKnown_A	584293779	584175214	0	0
RvalidKnown_A	584293779	584175214	0	0
WreadyKnown_A	584293779	584175214	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	42018	0	0
T4	143373	1	0	0
T5	245462	58	0	0
T6	406690	3	0	0
T17	197999	49	0	0
T18	205102	2	0	0
T19	153112	49	0	0
T42	271588	56	0	0
T53	204907	51	0	0
T54	121774	29	0	0
T86	77188	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584293779	584175214	0	0
T4	143373	143368	0	0
T5	245462	245349	0	0
T6	406690	406632	0	0
T17	197999	197987	0	0
T18	205102	204927	0	0
T19	153112	153100	0	0
T42	271588	271472	0	0
T53	204907	204901	0	0
T54	121774	121768	0	0
T86	77188	77126	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T42	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T86	1	1	0	0