Toggle Coverage for Module :
sysrst_ctrl
| Total | Covered | Percent |
Totals |
50 |
50 |
100.00 |
Total Bits |
334 |
334 |
100.00 |
Total Bits 0->1 |
167 |
167 |
100.00 |
Total Bits 1->0 |
167 |
167 |
100.00 |
| | | |
Ports |
50 |
50 |
100.00 |
Port Bits |
334 |
334 |
100.00 |
Port Bits 0->1 |
167 |
167 |
100.00 |
Port Bits 1->0 |
167 |
167 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
clk_aon_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T17,T42 |
Yes |
T4,T5,T6 |
INPUT |
rst_aon_ni |
Yes |
Yes |
T5,T17,T42 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T126,T330,T46 |
Yes |
T126,T330,T46 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T126,T330,T46 |
Yes |
T126,T330,T46 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[7:0] |
Yes |
Yes |
*T75,*T76,*T77 |
Yes |
T75,T76,T77 |
INPUT |
tl_i.a_address[15:8] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[17:16] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[21:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[22] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:23] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T58,*T68,*T78 |
Yes |
T58,T68,T78 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T75,T76,T77 |
Yes |
T75,T76,T77 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T79,T80,T81 |
Yes |
T79,T80,T81 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T126,T59,T330 |
Yes |
T126,T59,T330 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T126,T59,T330 |
Yes |
T126,T59,T330 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T75,T76,T77 |
Yes |
T75,T76,T77 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T126,T330,T46 |
Yes |
T126,T330,T46 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T126,T330,T46 |
Yes |
T126,T59,T330 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T126,T330,T46 |
Yes |
T126,T59,T330 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T75,T76,T77 |
Yes |
T75,T76,T77 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T81,*T75,*T76 |
Yes |
T81,T75,T76 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T75,T76,T77 |
Yes |
T75,T76,T77 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T126,*T330,*T46 |
Yes |
T126,T330,T46 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T126,T59,T330 |
Yes |
T126,T59,T330 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T59,T82,T220 |
Yes |
T59,T82,T220 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T82,T83,T85 |
Yes |
T82,T83,T85 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T82,T83,T85 |
Yes |
T82,T83,T85 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T59,T82,T220 |
Yes |
T59,T82,T220 |
OUTPUT |
wkup_req_o |
Yes |
Yes |
T126,T330,T1 |
Yes |
T126,T330,T46 |
OUTPUT |
rst_req_o |
Yes |
Yes |
T126,T330,T475 |
Yes |
T126,T330,T475 |
OUTPUT |
intr_event_detected_o |
Yes |
Yes |
T343,T205,T341 |
Yes |
T343,T205,T341 |
OUTPUT |
cio_ac_present_i |
Yes |
Yes |
T202,T33,T203 |
Yes |
T202,T33,T203 |
INPUT |
cio_ec_rst_l_i |
Yes |
Yes |
T32,T202,T33 |
Yes |
T32,T202,T33 |
INPUT |
cio_key0_in_i |
Yes |
Yes |
T126,T330,T475 |
Yes |
T126,T330,T475 |
INPUT |
cio_key1_in_i |
Yes |
Yes |
T32,T202,T33 |
Yes |
T32,T202,T33 |
INPUT |
cio_key2_in_i |
Yes |
Yes |
T202,T33,T34 |
Yes |
T202,T33,T34 |
INPUT |
cio_pwrb_in_i |
Yes |
Yes |
T1,T2,T202 |
Yes |
T1,T2,T202 |
INPUT |
cio_lid_open_i |
Yes |
Yes |
T202,T33,T47 |
Yes |
T46,T202,T33 |
INPUT |
cio_flash_wp_l_i |
Yes |
Yes |
T32,T33,T34 |
Yes |
T46,T32,T202 |
INPUT |
cio_bat_disable_o |
Yes |
Yes |
T126,T330,T475 |
Yes |
T126,T330,T475 |
OUTPUT |
cio_flash_wp_l_o |
Yes |
Yes |
T32,T33,T34 |
Yes |
T46,T32,T33 |
OUTPUT |
cio_ec_rst_l_o |
Yes |
Yes |
T32,T33,T34 |
Yes |
T32,T33,T34 |
OUTPUT |
cio_key0_out_o |
Yes |
Yes |
T126,T330,T475 |
Yes |
T126,T330,T475 |
OUTPUT |
cio_key1_out_o |
Yes |
Yes |
T32,T202,T33 |
Yes |
T32,T202,T33 |
OUTPUT |
cio_key2_out_o |
Yes |
Yes |
T202,T33,T34 |
Yes |
T32,T202,T33 |
OUTPUT |
cio_pwrb_out_o |
Yes |
Yes |
T1,T2,T202 |
Yes |
T1,T2,T32 |
OUTPUT |
cio_z3_wakeup_o |
Yes |
Yes |
T33,T34,T204 |
Yes |
T46,T32,T33 |
OUTPUT |
cio_bat_disable_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_flash_wp_l_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_ec_rst_l_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_key0_out_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_key1_out_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_key2_out_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_pwrb_out_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_z3_wakeup_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
*Tests covering at least one bit in the range