Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_uart0 100.00 100.00
tb.dut.top_earlgrey.u_uart1 100.00 100.00
tb.dut.top_earlgrey.u_uart2 100.00 100.00
tb.dut.top_earlgrey.u_uart3 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.37 90.68 89.43 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.37 90.68 89.43 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.37 90.68 89.43 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.37 90.68 89.43 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : uart
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T42 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T17,T53,T54 Yes T17,T53,T54 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T17,T53,T54 Yes T17,T53,T54 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T58,*T68,*T78 Yes T58,T68,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T79,T80,T81 Yes T79,T80,T81 INPUT
tl_i.a_valid Yes Yes T17,T53,T54 Yes T17,T53,T54 INPUT
tl_o.a_ready Yes Yes T17,T53,T54 Yes T17,T53,T54 OUTPUT
tl_o.d_error Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T17,T19,T188 Yes T17,T19,T188 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T17,T19,T188 Yes T17,T53,T54 OUTPUT
tl_o.d_data[31:0] Yes Yes T17,T19,T188 Yes T17,T53,T54 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[5:0] Yes Yes *T68,*T278,*T756 Yes T68,T278,T756 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T17,*T19,*T188 Yes T17,T19,T188 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T17,T53,T54 Yes T17,T53,T54 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T42,T59,T82 Yes T42,T59,T82 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T100,T83 Yes T82,T83,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T83,T85 Yes T82,T100,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T42,T59,T82 Yes T42,T59,T82 OUTPUT
cio_rx_i Yes Yes T5,T17,T42 Yes T4,T5,T6 INPUT
cio_tx_o Yes Yes T17,T19,T211 Yes T17,T19,T211 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T188,T211,T147 Yes T188,T211,T147 OUTPUT
intr_tx_empty_o Yes Yes T211,T147,T122 Yes T211,T147,T122 OUTPUT
intr_rx_watermark_o Yes Yes T211,T147,T122 Yes T211,T147,T122 OUTPUT
intr_tx_done_o Yes Yes T211,T147,T122 Yes T211,T147,T122 OUTPUT
intr_rx_overflow_o Yes Yes T211,T147,T122 Yes T211,T147,T122 OUTPUT
intr_rx_frame_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_break_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_timeout_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_parity_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 304 304 100.00
Total Bits 0->1 152 152 100.00
Total Bits 1->0 152 152 100.00

Ports 40 40 100.00
Port Bits 304 304 100.00
Port Bits 0->1 152 152 100.00
Port Bits 1->0 152 152 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T42 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T17,T53,T54 Yes T17,T53,T54 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T17,T53,T54 Yes T17,T53,T54 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 INPUT
tl_i.a_address[29:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T58,*T68,*T78 Yes T58,T68,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T79,T80,T81 Yes T79,T80,T81 INPUT
tl_i.a_valid Yes Yes T17,T53,T54 Yes T17,T53,T54 INPUT
tl_o.a_ready Yes Yes T17,T53,T54 Yes T17,T53,T54 OUTPUT
tl_o.d_error Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T17,T19,T188 Yes T17,T19,T188 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T17,T19,T188 Yes T17,T53,T54 OUTPUT
tl_o.d_data[31:0] Yes Yes T17,T19,T188 Yes T17,T53,T54 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[5:0] Yes Yes *T68,*T278,*T756 Yes T68,T278,T756 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T17,*T19,*T188 Yes T17,T19,T188 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T17,T53,T54 Yes T17,T53,T54 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T42,T59,T82 Yes T42,T59,T82 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T83,T85 Yes T82,T83,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T83,T85 Yes T82,T83,T85 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T42,T59,T82 Yes T42,T59,T82 OUTPUT
cio_rx_i Yes Yes T5,T17,T42 Yes T4,T5,T6 INPUT
cio_tx_o Yes Yes T17,T19,T68 Yes T17,T19,T68 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T188,T215,T247 Yes T188,T215,T247 OUTPUT
intr_tx_empty_o Yes Yes T215,T216,T217 Yes T215,T216,T217 OUTPUT
intr_rx_watermark_o Yes Yes T215,T216,T217 Yes T215,T216,T217 OUTPUT
intr_tx_done_o Yes Yes T353,T215,T354 Yes T353,T215,T354 OUTPUT
intr_rx_overflow_o Yes Yes T353,T215,T354 Yes T353,T215,T354 OUTPUT
intr_rx_frame_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_break_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_timeout_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_parity_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T42 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T211,T212,T343 Yes T211,T212,T343 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T211,T212,T343 Yes T211,T212,T343 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T58,*T68,*T78 Yes T58,T68,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T79,T80,T81 Yes T79,T80,T81 INPUT
tl_i.a_valid Yes Yes T59,T211,T212 Yes T59,T211,T212 INPUT
tl_o.a_ready Yes Yes T59,T211,T212 Yes T59,T211,T212 OUTPUT
tl_o.d_error Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T211,T212,T343 Yes T211,T212,T343 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T211,T212,T313 Yes T59,T211,T212 OUTPUT
tl_o.d_data[31:0] Yes Yes T211,T212,T313 Yes T59,T211,T212 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T211,*T212,*T343 Yes T211,T212,T343 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T59,T211,T212 Yes T59,T211,T212 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T59,T82,T83 Yes T59,T82,T83 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T83,T85 Yes T82,T85,T449 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T85,T449 Yes T82,T83,T85 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T59,T82,T83 Yes T59,T82,T83 OUTPUT
cio_rx_i Yes Yes T43,T211,T212 Yes T43,T211,T212 INPUT
cio_tx_o Yes Yes T211,T212,T375 Yes T211,T212,T375 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T211,T212,T343 Yes T211,T212,T343 OUTPUT
intr_tx_empty_o Yes Yes T211,T212,T343 Yes T211,T212,T343 OUTPUT
intr_rx_watermark_o Yes Yes T211,T212,T343 Yes T211,T212,T343 OUTPUT
intr_tx_done_o Yes Yes T211,T212,T343 Yes T211,T212,T343 OUTPUT
intr_rx_overflow_o Yes Yes T211,T212,T343 Yes T211,T212,T343 OUTPUT
intr_rx_frame_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_break_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_timeout_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_parity_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T42 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T147,T122,T210 Yes T147,T122,T210 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T147,T122,T210 Yes T147,T122,T210 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 INPUT
tl_i.a_address[16:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T58,*T68,*T78 Yes T58,T68,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T79,T80,T81 Yes T79,T80,T81 INPUT
tl_i.a_valid Yes Yes T59,T147,T122 Yes T59,T147,T122 INPUT
tl_o.a_ready Yes Yes T59,T147,T122 Yes T59,T147,T122 OUTPUT
tl_o.d_error Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T147,T122,T210 Yes T147,T122,T210 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T147,T122,T210 Yes T59,T147,T122 OUTPUT
tl_o.d_data[31:0] Yes Yes T147,T122,T210 Yes T59,T147,T122 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T147,*T122,*T210 Yes T147,T122,T210 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T59,T147,T122 Yes T59,T147,T122 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T59,T82,T389 Yes T59,T82,T389 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T100,T83 Yes T82,T83,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T83,T85 Yes T82,T100,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T59,T82,T389 Yes T59,T82,T389 OUTPUT
cio_rx_i Yes Yes T147,T122,T210 Yes T147,T122,T210 INPUT
cio_tx_o Yes Yes T147,T122,T210 Yes T147,T122,T210 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T147,T122,T210 Yes T147,T122,T210 OUTPUT
intr_tx_empty_o Yes Yes T147,T122,T210 Yes T147,T122,T210 OUTPUT
intr_rx_watermark_o Yes Yes T147,T122,T210 Yes T147,T122,T210 OUTPUT
intr_tx_done_o Yes Yes T147,T122,T210 Yes T147,T122,T210 OUTPUT
intr_rx_overflow_o Yes Yes T147,T122,T210 Yes T147,T122,T210 OUTPUT
intr_rx_frame_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_break_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_timeout_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_parity_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T42 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T26,T28,T342 Yes T26,T28,T342 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T26,T28,T342 Yes T26,T28,T342 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T58,*T68,*T78 Yes T58,T68,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T79,T80,T81 Yes T79,T80,T81 INPUT
tl_i.a_valid Yes Yes T59,T26,T60 Yes T59,T26,T60 INPUT
tl_o.a_ready Yes Yes T59,T26,T60 Yes T59,T26,T60 OUTPUT
tl_o.d_error Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T26,T28,T342 Yes T26,T28,T342 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T26,T28,T342 Yes T59,T26,T60 OUTPUT
tl_o.d_data[31:0] Yes Yes T26,T28,T342 Yes T59,T26,T60 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T26,*T28,*T342 Yes T26,T28,T342 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T59,T26,T60 Yes T59,T26,T60 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T59,T82,T736 Yes T59,T82,T736 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T83,T85 Yes T82,T83,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T83,T85 Yes T82,T83,T85 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T59,T82,T736 Yes T59,T82,T736 OUTPUT
cio_rx_i Yes Yes T26,T28,T342 Yes T26,T28,T342 INPUT
cio_tx_o Yes Yes T26,T28,T342 Yes T26,T28,T342 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T26,T28,T342 Yes T26,T28,T342 OUTPUT
intr_tx_empty_o Yes Yes T26,T28,T342 Yes T26,T28,T342 OUTPUT
intr_rx_watermark_o Yes Yes T26,T28,T342 Yes T26,T28,T342 OUTPUT
intr_tx_done_o Yes Yes T26,T28,T342 Yes T26,T28,T342 OUTPUT
intr_rx_overflow_o Yes Yes T26,T28,T342 Yes T26,T28,T342 OUTPUT
intr_rx_frame_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_break_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_timeout_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT
intr_rx_parity_err_o Yes Yes T343,T341,T344 Yes T343,T341,T344 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%