Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic	75.00		100.00				50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00		100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_por_aon_n_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T43,T23,T32
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T43,T23
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T43,T23,T32

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	24183	23808	0	0
selKnown1	38773	37484	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	24183	23808	0	0
T18	3	2	0	0
T20	2	0	0	0
T21	2	0	0	0
T23	4550	4548	0	0
T24	98	96	0	0
T25	5375	5373	0	0
T27	32	31	0	0
T39	5	0	0	0
T40	22	20	0	0
T41	3	7	0	0
T45	0	12	0	0
T55	2	1	0	0
T56	2	1	0	0
T57	1	0	0	0
T58	1	0	0	0
T63	3	2	0	0
T65	0	5	0	0
T68	1	0	0	0
T71	40	39	0	0
T72	0	21	0	0
T118	1	0	0	0
T119	0	2	0	0
T120	0	5	0	0
T189	2513	2511	0	0
T190	4353	4351	0	0
T191	1865	1863	0	0
T192	0	5	0	0
T193	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	38773	37484	0	0
T5	2	1	0	0
T6	1	0	0	0
T17	2	1	0	0
T18	3	2	0	0
T19	2	1	0	0
T39	29	27	0	0
T40	28	48	0	0
T41	18	35	0	0
T42	2	1	0	0
T43	545	544	0	0
T45	6	13	0	0
T53	1	0	0	0
T54	1	0	0	0
T64	0	1	0	0
T86	1	0	0	0
T116	0	1	0	0
T126	0	2	0	0
T156	1	0	0	0
T169	0	1	0	0
T188	0	4	0	0
T192	6	11	0	0
T193	19	48	0	0
T194	6	15	0	0
T195	18	36	0	0
T196	5	4	0	0
T197	9	8	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T43,T23,T25
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	1247	1228	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1247	1228	0	0
T20	1	0	0	0
T21	1	0	0	0
T23	1	0	0	0
T25	1	0	0	0
T39	17	16	0	0
T40	0	21	0	0
T41	0	18	0	0
T43	545	544	0	0
T44	545	544	0	0
T45	0	8	0	0
T189	1	0	0	0
T190	1	0	0	0
T191	1	0	0	0
T192	0	6	0	0
T193	0	30	0	0
T194	0	10	0	0
T195	0	19	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T20
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[4].gen_mux_spi_host_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	132	117	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	132	117	0	0
T39	12	11	0	0
T40	28	27	0	0
T41	18	17	0	0
T45	6	5	0	0
T192	6	5	0	0
T193	19	18	0	0
T194	6	5	0	0
T195	18	17	0	0
T196	5	4	0	0
T197	9	8	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T43,T24,T44
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	158	144	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	158	144	0	0
T22	1	0	0	0
T24	1	0	0	0
T39	17	16	0	0
T40	19	18	0	0
T41	25	24	0	0
T43	2	1	0	0
T44	2	1	0	0
T45	10	9	0	0
T192	11	10	0	0
T193	18	17	0	0
T194	0	14	0	0
T195	0	16	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T20
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].gen_mux_spi_host_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	143	129	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	143	129	0	0
T39	14	13	0	0
T40	22	21	0	0
T41	20	19	0	0
T45	10	9	0	0
T192	9	8	0	0
T193	20	19	0	0
T194	12	11	0	0
T195	17	16	0	0
T196	10	9	0	0
T197	5	4	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T20,T39,T40
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	138	127	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	138	127	0	0
T39	9	8	0	0
T40	32	31	0	0
T41	18	17	0	0
T45	7	6	0	0
T192	14	13	0	0
T193	18	17	0	0
T194	13	12	0	0
T195	17	16	0	0
T196	3	2	0	0
T197	6	5	0	0

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Unreachable

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].gen_mux_spi_device_sd2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	0	0	0	0
selKnown1	116	103	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	116	103	0	0
T39	11	10	0	0
T40	20	19	0	0
T41	12	11	0	0
T45	8	7	0	0
T192	9	8	0	0
T193	19	18	0	0
T194	7	6	0	0
T195	17	16	0	0
T196	3	2	0	0
T197	7	6	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T57,T58
0	1	Covered	T18,T57,T58
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T57,T58
1	1	Covered	T18,T57,T58

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	770	643	0	0
selKnown1	1761	762	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	770	643	0	0
T18	3	2	0	0
T27	32	31	0	0
T55	2	1	0	0
T56	2	1	0	0
T57	1	0	0	0
T58	1	0	0	0
T63	3	2	0	0
T65	0	5	0	0
T68	1	0	0	0
T71	40	39	0	0
T72	0	21	0	0
T118	1	0	0	0
T119	0	2	0	0
T120	0	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1761	762	0	0
T5	2	1	0	0
T6	1	0	0	0
T17	2	1	0	0
T18	3	2	0	0
T19	2	1	0	0
T42	2	1	0	0
T53	1	0	0	0
T54	1	0	0	0
T64	0	1	0	0
T86	1	0	0	0
T116	0	1	0	0
T126	0	2	0	0
T156	1	0	0	0
T169	0	1	0	0
T188	0	4	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T23,T24,T25
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T39
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T23,T24,T25

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	18680	18662	0	0
selKnown1	410	398	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	18680	18662	0	0
T20	1	0	0	0
T21	1	0	0	0
T23	4537	4536	0	0
T24	97	96	0	0
T25	5362	5361	0	0
T39	5	4	0	0
T40	18	17	0	0
T41	0	5	0	0
T45	0	10	0	0
T189	2437	2436	0	0
T190	4337	4336	0	0
T191	1789	1788	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	410	398	0	0
T39	16	15	0	0
T40	16	15	0	0
T41	14	13	0	0
T43	115	114	0	0
T44	156	155	0	0
T45	14	13	0	0
T192	14	13	0	0
T193	18	17	0	0
T194	10	9	0	0
T195	21	20	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T23,T24,T25
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T39
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T23,T24,T25

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].gen_mux_spi_device_sd3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	238	220	0	0
selKnown1	127	115	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	238	220	0	0
T20	1	0	0	0
T21	1	0	0	0
T23	13	12	0	0
T24	1	0	0	0
T25	13	12	0	0
T40	4	3	0	0
T41	3	2	0	0
T45	0	2	0	0
T189	76	75	0	0
T190	16	15	0	0
T191	76	75	0	0
T192	0	5	0	0
T193	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	127	115	0	0
T39	8	7	0	0
T40	15	14	0	0
T41	15	14	0	0
T45	12	11	0	0
T192	14	13	0	0
T193	16	15	0	0
T194	10	9	0	0
T195	20	19	0	0
T196	9	8	0	0
T197	6	5	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T79
0	1	Covered	T43,T24,T44
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T43,T44,T79
1	1	Covered	T43,T24,T44

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1289	1268	0	0
selKnown1	54	33	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1289	1268	0	0
T20	1	0	0	0
T21	1	0	0	0
T24	1	0	0	0
T39	0	10	0	0
T40	0	11	0	0
T41	0	10	0	0
T43	546	545	0	0
T44	546	545	0	0
T45	0	15	0	0
T79	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T192	0	16	0	0
T193	0	21	0	0
T194	0	24	0	0
T195	0	36	0	0
T198	1	0	0	0
T199	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	54	33	0	0
T20	2	1	0	0
T21	2	1	0	0
T22	2	1	0	0
T39	4	3	0	0
T40	4	3	0	0
T41	4	3	0	0
T45	4	3	0	0
T74	1	0	0	0
T192	0	3	0	0
T193	0	3	0	0
T194	0	3	0	0
T200	1	0	0	0
T201	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T79
0	1	Covered	T43,T24,T44
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T43,T44,T79
1	1	Covered	T43,T24,T44

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1292	1271	0	0
selKnown1	54	33	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292	1271	0	0
T20	1	0	0	0
T21	1	0	0	0
T24	1	0	0	0
T39	0	10	0	0
T40	0	11	0	0
T41	0	11	0	0
T43	546	545	0	0
T44	546	545	0	0
T45	0	17	0	0
T79	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T192	0	18	0	0
T193	0	22	0	0
T194	0	22	0	0
T195	0	36	0	0
T198	1	0	0	0
T199	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	54	33	0	0
T20	2	1	0	0
T21	2	1	0	0
T22	2	1	0	0
T39	4	3	0	0
T40	4	3	0	0
T41	4	3	0	0
T45	4	3	0	0
T74	1	0	0	0
T192	0	3	0	0
T193	0	3	0	0
T194	0	3	0	0
T200	1	0	0	0
T201	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T79
0	1	Covered	T43,T23,T24
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T43,T44,T79
1	1	Covered	T43,T23,T24

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	204	178	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	204	178	0	0
T23	1	0	0	0
T24	1	0	0	0
T25	1	0	0	0
T39	0	21	0	0
T40	0	19	0	0
T41	0	11	0	0
T43	2	1	0	0
T44	2	1	0	0
T45	0	22	0	0
T79	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T189	1	0	0	0
T190	1	0	0	0
T192	0	21	0	0
T193	0	13	0	0
T194	0	24	0	0
T195	0	23	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T20	2	1	0	0
T21	2	1	0	0
T22	2	1	0	0
T74	1	0	0	0
T200	1	0	0	0
T201	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T79
0	1	Covered	T43,T23,T24
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T43,T44,T79
1	1	Covered	T43,T23,T24

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	201	175	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	201	175	0	0
T23	1	0	0	0
T24	1	0	0	0
T25	1	0	0	0
T39	0	20	0	0
T40	0	19	0	0
T41	0	12	0	0
T43	2	1	0	0
T44	2	1	0	0
T45	0	24	0	0
T79	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T189	1	0	0	0
T190	1	0	0	0
T192	0	19	0	0
T193	0	13	0	0
T194	0	26	0	0
T195	0	21	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T20	2	1	0	0
T21	2	1	0	0
T22	2	1	0	0
T74	1	0	0	0
T200	1	0	0	0
T201	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T62,T79,T80
0	1	Covered	T20,T39,T40
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T62,T79,T80
1	1	Covered	T20,T39,T40

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	167	150	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	167	150	0	0
T39	9	8	0	0
T40	11	10	0	0
T41	18	17	0	0
T45	24	23	0	0
T192	10	9	0	0
T193	24	23	0	0
T194	26	25	0	0
T195	14	13	0	0
T196	14	13	0	0
T197	10	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T20	2	1	0	0
T21	2	1	0	0
T22	2	1	0	0
T74	1	0	0	0
T200	1	0	0	0
T201	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T62,T79,T80
0	1	Covered	T20,T39,T40
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T62,T79,T80
1	1	Covered	T20,T39,T40

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	170	153	0	0
selKnown1	24	3	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	170	153	0	0
T39	9	8	0	0
T40	11	10	0	0
T41	18	17	0	0
T45	24	23	0	0
T192	11	10	0	0
T193	25	24	0	0
T194	26	25	0	0
T195	16	15	0	0
T196	13	12	0	0
T197	10	9	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	24	3	0	0
T20	2	1	0	0
T21	2	1	0	0
T22	2	1	0	0
T74	1	0	0	0
T200	1	0	0	0
T201	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T43,T32,T202
0	1	Covered	T43,T23,T32
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T43,T23,T24
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T43,T32,T202
1	1	Covered	T43,T23,T32

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	588	546	0	0
selKnown1	17168	17141	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	588	546	0	0
T23	1	0	0	0
T24	1	0	0	0
T25	1	0	0	0
T32	1	0	0	0
T33	2	1	0	0
T34	8	7	0	0
T43	112	111	0	0
T44	0	150	0	0
T202	2	1	0	0
T203	2	1	0	0
T204	8	7	0	0
T205	0	33	0	0
T206	0	7	0	0
T207	0	25	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	17168	17141	0	0
T23	4516	4515	0	0
T24	95	94	0	0
T25	5297	5296	0	0
T39	0	6	0	0
T40	0	11	0	0
T41	0	8	0	0
T44	1	0	0	0
T45	0	3	0	0
T79	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T189	1563	1562	0	0
T190	4272	4271	0	0
T191	0	1316	0	0
T198	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T43,T32,T202
0	1	Covered	T43,T23,T32
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T43,T23,T24
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T43,T32,T202
1	1	Covered	T43,T23,T32

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	584	542	0	0
selKnown1	17169	17142	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	584	542	0	0
T23	1	0	0	0
T24	1	0	0	0
T25	1	0	0	0
T32	1	0	0	0
T33	2	1	0	0
T34	8	7	0	0
T43	112	111	0	0
T44	0	150	0	0
T202	2	1	0	0
T203	2	1	0	0
T204	8	7	0	0
T205	0	33	0	0
T206	0	7	0	0
T207	0	25	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	17169	17142	0	0
T23	4516	4515	0	0
T24	95	94	0	0
T25	5297	5296	0	0
T39	0	6	0	0
T40	0	12	0	0
T41	0	8	0	0
T44	1	0	0	0
T45	0	3	0	0
T79	1	0	0	0
T80	1	0	0	0
T81	1	0	0	0
T189	1563	1562	0	0
T190	4272	4271	0	0
T191	0	1316	0	0
T198	1	0	0	0