Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.37	90.68		89.43			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T75,T77,T271	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T75,T77,T272	Yes	T75,T77,T272	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T58,T220,T68	Yes	T58,T220,T68	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T58,T220,T68	Yes	T58,T220,T68	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T80,T199,T75	Yes	T80,T199,T75	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T80,T199,T75	Yes	T80,T199,T75	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T5,T64,T58	Yes	T5,T64,T58	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T5,T42,T18	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T58,T68,T65	Yes	T58,T68,T65	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T42,T18	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T5,T42,T18	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T58,T68,T65	Yes	T58,T68,T65	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T5,T42,T18	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T58,T68,T65	Yes	T58,T68,T65	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T58,T68,T65	Yes	T58,T68,T65	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T68,T65,T66	Yes	T68,T65,T66	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T58,T68,T65	Yes	T58,T68,T65	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T58,*T68,*T65	Yes	T58,T68,T65	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T58,T68,T65	Yes	T58,T68,T65	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T9,T75,T76	Yes	T9,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T9,T75,T77	Yes	T9,T75,T76	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T9,T75,T76	Yes	T9,T75,T76	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T9,*T75,*T76	Yes	T9,T75,T76	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T58,T68,T78	Yes	T58,T68,T78	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T68,T78	Yes	T58,T68,T78	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T58,T68,T78	Yes	T58,T68,T78	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T58,T68,T78	Yes	T58,T68,T78	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T58,T68,T78	Yes	T58,T68,T78	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T58,*T68,*T78	Yes	T58,T68,T78	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T58,T68,T78	Yes	T58,T68,T78	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T42,T18	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T58,T68,T78	Yes	T58,T68,T78	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T58,T68,T78	Yes	T58,T68,T78	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T42,T18	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T58,*T68,*T78	Yes	T58,T68,T78	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T42,T18	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T58,T68,T78	Yes	T58,T68,T78	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T17,T53,T54	Yes	T17,T53,T54	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T9,*T75,*T76	Yes	T9,T75,T76	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T290,T455,T456	Yes	T290,T455,T456	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T75,T76	Yes	T59,T60,T61	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T290,T455,T456	Yes	T59,T60,T61	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T9,T75,T76	Yes	T9,T75,T76	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T290,*T457,*T458	Yes	T290,T455,T456	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T58,*T68,*T78	Yes	T58,T68,T78	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T5,T42,T64	Yes	T5,T42,T64	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T58,*T68,*T78	Yes	T58,T68,T78	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T188,T23,T59	Yes	T188,T23,T59	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T23,T59,T60	Yes	T23,T59,T60	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T188,T23,T59	Yes	T188,T23,T59	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T188,T23,T59	Yes	T188,T23,T59	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T23,T59,T60	Yes	T23,T59,T60	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T188,T23,T59	Yes	T188,T23,T59	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T81,*T75,*T76	Yes	T81,T75,T76	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T189,T191,T75	Yes	T189,T191,T75	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T188,T23,T59	Yes	T188,T23,T59	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T188,T23,T59	Yes	T188,T23,T59	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T23,T396,T24	Yes	T23,T396,T24	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T188,T23,T396	Yes	T188,T23,T59	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T23,T396,T24	Yes	T23,T396,T24	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T81,*T75,*T76	Yes	T81,T75,T76	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T188,*T23,*T396	Yes	T188,T23,T396	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T188,T23,T59	Yes	T188,T23,T59	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T43,T188,T59	Yes	T43,T188,T59	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T43,T59,T60	Yes	T43,T59,T60	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T43,T188,T59	Yes	T43,T188,T59	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T43,T188,T59	Yes	T43,T188,T59	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T43,T59,T60	Yes	T43,T59,T60	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T43,T188,T59	Yes	T43,T188,T59	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T81,*T75,*T76	Yes	T81,T75,T76	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T43,T188,T59	Yes	T43,T188,T59	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T43,T188,T59	Yes	T43,T188,T59	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T75,T76,T77	Yes	T76,T77,T272	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T43,T396,T408	Yes	T43,T396,T408	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T43,T188,T396	Yes	T43,T188,T59	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T43,T396,T408	Yes	T43,T396,T408	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T81,*T75,*T76	Yes	T81,T75,T76	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T43,*T188,*T396	Yes	T43,T188,T396	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T43,T188,T59	Yes	T43,T188,T59	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T29,T188,T59	Yes	T29,T188,T59	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T29,T188,T59	Yes	T29,T188,T59	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T29,T188,T59	Yes	T29,T188,T59	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T29,T188,T59	Yes	T29,T188,T59	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T29,T59,T1	Yes	T29,T59,T1	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T29,T188,T59	Yes	T29,T188,T59	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T29,T188,T59	Yes	T29,T188,T59	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T29,T188,T59	Yes	T29,T188,T59	INPUT
tl_usbdev_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T29,T188,T30	Yes	T29,T188,T30	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T188,T30	Yes	T29,T188,T30	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T29,T188,T59	Yes	T29,T188,T30	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T29,*T188,*T59	Yes	T29,T188,T30	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T29,T188,T59	Yes	T29,T188,T59	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T17,T42	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T79,*T81,T75	Yes	T79,T81,T75	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T79,*T81,T75	Yes	T79,T81,T75	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T79,T81,T75	Yes	T79,T81,T75	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T17,T42	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T115,T753,T310	Yes	T115,T753,T310	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	INPUT
tl_hmac_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	INPUT
tl_hmac_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T6,*T17,*T53	Yes	T6,T17,T53	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T6,T17,T53	Yes	T6,T17,T53	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T308,T59,T117	Yes	T308,T59,T117	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T308,T59,T113	Yes	T308,T59,T113	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T308,T59,T113	Yes	T308,T59,T113	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T308,T59,T117	Yes	T308,T59,T117	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T308,T59,T113	Yes	T308,T59,T113	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T79,*T81,*T9	Yes	T79,T81,T9	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T308,T464,T465	Yes	T308,T464,T465	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T308,T59,T113	Yes	T308,T59,T113	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T308,T59,T113	Yes	T308,T59,T113	INPUT
tl_kmac_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T308,T113,T117	Yes	T308,T113,T117	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T308,T113,T117	Yes	T308,T113,T117	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T308,T59,T113	Yes	T308,T128,T224	INPUT
tl_kmac_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T9	Yes	T79,T81,T9	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T308,*T59,*T113	Yes	T308,T128,T224	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T308,T59,T113	Yes	T308,T59,T113	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T17,T86	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T86,T59,T113	Yes	T86,T59,T113	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T86,T59,T113	Yes	T86,T59,T113	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T86,T59,T113	Yes	T86,T59,T113	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T86,T59,T113	Yes	T86,T59,T113	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T86,T59,T113	Yes	T86,T59,T113	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T86,T59,T113	Yes	T86,T59,T113	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T86,T59,T113	Yes	T86,T59,T113	INPUT
tl_aes_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T86,T113,T130	Yes	T86,T113,T130	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T86,T113,T130	Yes	T86,T59,T113	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T86,T130,T391	Yes	T86,T59,T113	INPUT
tl_aes_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T86,*T113,*T130	Yes	T86,T113,T130	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T86,T59,T113	Yes	T86,T59,T113	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T113	Yes	T4,T6,T113	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T113	Yes	T4,T6,T53	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T4,T6,T712	Yes	T4,T6,T712	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T712	Yes	T4,T6,T712	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T712	Yes	T4,T6,T712	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T113	Yes	T4,T6,T113	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T113	Yes	T4,T6,T113	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_edn1_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T113	Yes	T4,T6,T113	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T113	Yes	T4,T6,T59	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T4,T6,T113	Yes	T4,T6,T59	INPUT
tl_edn1_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T113	Yes	T4,T6,T113	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T81,*T75,*T76	Yes	T81,T75,T76	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T76,T77,T208	Yes	T76,T77,T208	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T42	Yes	T5,T6,T42	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T81,*T75,*T76	Yes	T81,T75,T76	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T80,*T198,*T199	Yes	T80,T198,T199	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T76,T77,T208	Yes	T76,T77,T208	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	INPUT
tl_otbn_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	INPUT
tl_otbn_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T80,*T198,*T199	Yes	T80,T198,T199	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T76,T77,T208	Yes	T76,T77,T208	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T4,*T17,*T53	Yes	T4,T17,T53	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T4,T17,T53	Yes	T4,T17,T53	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T5,T17,T53	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T172,T59,T113	Yes	T172,T59,T113	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	INPUT
tl_keymgr_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T113,T56,T221	Yes	T113,T56,T221	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T53,*T54,*T172	Yes	T53,T54,T172	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T53,T54,T172	Yes	T53,T54,T172	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T278,*T9,*T75	Yes	T278,T9,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T9,T75,T76	Yes	T9,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T9,*T75,*T76	Yes	T278,T9,T75	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T5,T17,T53	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T17,T53,T54	Yes	T17,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T53,T54	Yes	T17,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T17,T53,T54	Yes	T17,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T17,T53,T54	Yes	T17,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T17,T53,T54	Yes	T17,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T81,*T459,*T460	Yes	T81,T459,T460	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T17,T53,T54	Yes	T17,T53,T54	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T17,T53,T54	Yes	T17,T53,T54	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T184,T337,T81	Yes	T184,T337,T81	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T19,T116	Yes	T17,T53,T54	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T17,T19,T116	Yes	T17,T53,T54	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T81,*T75,*T76	Yes	T81,T459,T460	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T116,*T184,*T337	Yes	T116,T325,T184	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T17,T53,T54	Yes	T17,T53,T54	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T17,T42	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range