Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26			99.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_edn1	99.02			99.02
tb.dut.top_earlgrey.u_edn0	99.17			99.17

---

Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.02			99.02

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.02			99.02

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.37	90.68		89.43			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17			99.17

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17			99.17

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.37	90.68		89.43			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	78	74	94.87
Total Bits	1210	1201	99.26
Total Bits 0->1	605	602	99.50
Total Bits 1->0	605	599	99.01

Ports	78	74	94.87
Port Bits	1210	1201	99.26
Port Bits 0->1	605	602	99.50
Port Bits 1->0	605	599	99.01

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:16]	Yes	Yes	T4,*T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T113	Yes	T4,T6,T113	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T113	Yes	T4,T6,T113	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i[0].edn_req	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[2].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[3].edn_req	Yes	Yes	T113,T152,T465	Yes	T113,T152,T465	INPUT
edn_i[4].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[5].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[6].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[7].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T130,T279,T468	Yes	T4,T113,T130	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T4,T152,T114	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T110,T111,T112	Yes	T4,T113,T114	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T113,T152,T465	Yes	T113,T152,T465	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T113,T152,T417	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T113,T152,T465	Yes	T113,T152,T465	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T4,T17,T19	Yes	T4,T6,T17	OUTPUT
edn_o[4].edn_fips	No	No		Yes	T4,T707,T708	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T130,T279,T468	Yes	T113,T130,T709	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T130,T279,T468	Yes	T4,T113,T130	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T130,T110,T279	Yes	T113,T130,T152	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T110,T401,T112	Yes	T4,T113,T130	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T130,T391,T129	Yes	T130,T391,T129	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T82,T391	Yes	T59,T82,T391	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T64,T59,T82	Yes	T64,T59,T82	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T82,T391	Yes	T59,T82,T391	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T64,T59,T82	Yes	T64,T59,T82	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T127,T101	Yes	T6,T127,T101	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T6,T345,T347	Yes	T6,T345,T347	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1

	Total	Covered	Percent
Totals	50	48	96.00
Total Bits	714	707	99.02
Total Bits 0->1	357	354	99.16
Total Bits 1->0	357	353	98.88

Ports	50	48	96.00
Port Bits	714	707	99.02
Port Bits 0->1	357	354	99.16
Port Bits 1->0	357	353	98.88

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:19]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T6,*T59	Yes	T4,T6,T59	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T59	Yes	T4,T6,T59	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_o.a_ready	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T113	Yes	T4,T6,T113	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T113	Yes	T4,T6,T59	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T6,T113	Yes	T4,T6,T59	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T113	Yes	T4,T6,T113	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	OUTPUT
edn_i[0].edn_req	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	INPUT
edn_i[1].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[2].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[3].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[4].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[5].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[6].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[7].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_o[0].edn_bus[31:0]	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T130,T279,T468	Yes	T4,T113,T130	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	OUTPUT
edn_o[1].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
csrng_cmd_o.genbits_ready	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	INPUT
csrng_cmd_i.genbits_fips	No	No		Yes	T401,T710,T711	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T4,T113,T130	Yes	T4,T113,T130	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T130,T279,T468	Yes	T130,T279,T468	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T82,T83	Yes	T59,T82,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T59,T82,T83	Yes	T59,T82,T83	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T82,T83	Yes	T59,T82,T83	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T59,T82,T83	Yes	T59,T82,T83	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T127,T101	Yes	T6,T127,T101	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T6,T345,T347	Yes	T6,T345,T347	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0

	Total	Covered	Percent
Totals	78	73	93.59
Total Bits	1208	1198	99.17
Total Bits 0->1	604	601	99.50
Total Bits 1->0	604	597	98.84

Ports	78	73	93.59
Port Bits	1208	1198	99.17
Port Bits 0->1	604	601	99.50
Port Bits 1->0	604	597	98.84

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T17,T42	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T59	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T113	Yes	T4,T6,T113	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T81,*T75	Yes	T79,T81,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T113	Yes	T4,T6,T113	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i[0].edn_req	Yes	Yes	T113,T56,T117	Yes	T113,T56,T117	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[2].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[3].edn_req	Yes	Yes	T113,T152,T465	Yes	T113,T152,T465	INPUT
edn_i[4].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[5].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[6].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_i[7].edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T113,T56,T117	Yes	T113,T56,T117	OUTPUT
edn_o[0].edn_fips	No	No		Yes	T113,T117,T102	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T113,T56,T117	Yes	T113,T56,T117	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T4,T152,T114	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T110,T111,T112	Yes	T4,T113,T114	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T113,T152,T465	Yes	T113,T152,T465	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T113,T152,T417	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T113,T152,T465	Yes	T113,T152,T465	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T4,T17,T19	Yes	T4,T6,T17	OUTPUT
edn_o[4].edn_fips	No	No		Yes	T4,T707,T708	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T130,T279,T468	Yes	T113,T130,T709	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T130,T279,T468	Yes	T4,T113,T130	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T130,T110,T279	Yes	T113,T130,T152	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T110,T401,T112	Yes	T4,T113,T130	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T130,T391,T129	Yes	T130,T391,T129	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T82,T391	Yes	T59,T82,T391	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T64,T59,T82	Yes	T64,T59,T82	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T82,T391	Yes	T59,T82,T391	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T64,T59,T82	Yes	T64,T59,T82	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T127,T101	Yes	T6,T127,T101	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T6,T345,T347	Yes	T6,T345,T347	OUTPUT

*Tests covering at least one bit in the range