Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T15,T9 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T3,T15,T9 |
1 | 1 | Covered | T3,T15,T9 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T3,T15,T9 |
1 | - | Covered | T3,T15,T16 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T15,T9 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T15,T9 |
1 | 1 | Covered | T3,T15,T9 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T3,T15,T9 |
0 |
0 |
1 |
Covered |
T3,T15,T9 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T3,T15,T9 |
0 |
0 |
1 |
Covered |
T3,T15,T9 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
102402 |
0 |
0 |
T3 |
44995 |
892 |
0 |
0 |
T9 |
0 |
344 |
0 |
0 |
T15 |
0 |
792 |
0 |
0 |
T16 |
0 |
878 |
0 |
0 |
T148 |
0 |
3978 |
0 |
0 |
T149 |
0 |
481 |
0 |
0 |
T150 |
0 |
831 |
0 |
0 |
T392 |
0 |
276 |
0 |
0 |
T393 |
0 |
2820 |
0 |
0 |
T394 |
0 |
2117 |
0 |
0 |
T417 |
103743 |
0 |
0 |
0 |
T418 |
24504 |
0 |
0 |
0 |
T419 |
83196 |
0 |
0 |
0 |
T420 |
64693 |
0 |
0 |
0 |
T421 |
70746 |
0 |
0 |
0 |
T422 |
147025 |
0 |
0 |
0 |
T423 |
97972 |
0 |
0 |
0 |
T424 |
64543 |
0 |
0 |
0 |
T425 |
17821 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
256 |
0 |
0 |
T3 |
44995 |
2 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T16 |
0 |
2 |
0 |
0 |
T148 |
0 |
10 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T392 |
0 |
1 |
0 |
0 |
T393 |
0 |
7 |
0 |
0 |
T394 |
0 |
6 |
0 |
0 |
T417 |
103743 |
0 |
0 |
0 |
T418 |
24504 |
0 |
0 |
0 |
T419 |
83196 |
0 |
0 |
0 |
T420 |
64693 |
0 |
0 |
0 |
T421 |
70746 |
0 |
0 |
0 |
T422 |
147025 |
0 |
0 |
0 |
T423 |
97972 |
0 |
0 |
0 |
T424 |
64543 |
0 |
0 |
0 |
T425 |
17821 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
0 |
1 |
156 |
0 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T426 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T9,T148,T149 |
1 | - | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
94707 |
0 |
0 |
T9 |
404309 |
272 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
1946 |
0 |
0 |
T149 |
0 |
438 |
0 |
0 |
T150 |
0 |
832 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
682 |
0 |
0 |
T393 |
0 |
2809 |
0 |
0 |
T394 |
0 |
2022 |
0 |
0 |
T395 |
0 |
3085 |
0 |
0 |
T415 |
0 |
465 |
0 |
0 |
T416 |
0 |
290 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
237 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
5 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T393 |
0 |
7 |
0 |
0 |
T394 |
0 |
6 |
0 |
0 |
T395 |
0 |
8 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
0 |
1 |
156 |
0 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T432 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T9,T148,T149 |
1 | - | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
108837 |
0 |
0 |
T9 |
404309 |
264 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
5967 |
0 |
0 |
T149 |
0 |
437 |
0 |
0 |
T150 |
0 |
2475 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
702 |
0 |
0 |
T393 |
0 |
277 |
0 |
0 |
T394 |
0 |
344 |
0 |
0 |
T395 |
0 |
1833 |
0 |
0 |
T415 |
0 |
389 |
0 |
0 |
T416 |
0 |
254 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
275 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
15 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
6 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T393 |
0 |
1 |
0 |
0 |
T394 |
0 |
1 |
0 |
0 |
T395 |
0 |
5 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T12,T9,T148 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T12,T9,T148 |
1 | 1 | Covered | T12,T9,T148 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T12,T9,T148 |
1 | - | Covered | T12 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T12,T9,T148 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T12,T9,T148 |
1 | 1 | Covered | T12,T9,T148 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T12,T9,T148 |
0 |
0 |
1 |
Covered |
T12,T9,T148 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T12,T9,T148 |
0 |
0 |
1 |
Covered |
T12,T9,T148 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
108681 |
0 |
0 |
T9 |
0 |
361 |
0 |
0 |
T12 |
19498 |
874 |
0 |
0 |
T88 |
58303 |
0 |
0 |
0 |
T148 |
0 |
5259 |
0 |
0 |
T149 |
0 |
420 |
0 |
0 |
T150 |
0 |
1503 |
0 |
0 |
T392 |
0 |
2178 |
0 |
0 |
T393 |
0 |
2827 |
0 |
0 |
T394 |
0 |
935 |
0 |
0 |
T395 |
0 |
1852 |
0 |
0 |
T415 |
0 |
460 |
0 |
0 |
T433 |
25867 |
0 |
0 |
0 |
T434 |
18101 |
0 |
0 |
0 |
T435 |
55109 |
0 |
0 |
0 |
T436 |
400702 |
0 |
0 |
0 |
T437 |
39685 |
0 |
0 |
0 |
T438 |
549898 |
0 |
0 |
0 |
T439 |
152632 |
0 |
0 |
0 |
T440 |
27790 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
275 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T12 |
19498 |
2 |
0 |
0 |
T88 |
58303 |
0 |
0 |
0 |
T148 |
0 |
13 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T392 |
0 |
6 |
0 |
0 |
T393 |
0 |
7 |
0 |
0 |
T394 |
0 |
3 |
0 |
0 |
T395 |
0 |
5 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T433 |
25867 |
0 |
0 |
0 |
T434 |
18101 |
0 |
0 |
0 |
T435 |
55109 |
0 |
0 |
0 |
T436 |
400702 |
0 |
0 |
0 |
T437 |
39685 |
0 |
0 |
0 |
T438 |
549898 |
0 |
0 |
0 |
T439 |
152632 |
0 |
0 |
0 |
T440 |
27790 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
0 |
1 |
156 |
0 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T9,T148,T149 |
1 | - | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
107384 |
0 |
0 |
T9 |
404309 |
323 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
5323 |
0 |
0 |
T149 |
0 |
478 |
0 |
0 |
T150 |
0 |
1181 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
2933 |
0 |
0 |
T393 |
0 |
1965 |
0 |
0 |
T394 |
0 |
3622 |
0 |
0 |
T395 |
0 |
607 |
0 |
0 |
T415 |
0 |
438 |
0 |
0 |
T416 |
0 |
269 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
270 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
13 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
3 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
8 |
0 |
0 |
T393 |
0 |
5 |
0 |
0 |
T394 |
0 |
10 |
0 |
0 |
T395 |
0 |
2 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T13 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Covered | T1,T2,T13 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T13 |
1 | - | Covered | T1,T2,T13 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T13 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Covered | T1,T2,T13 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T13 |
0 |
0 |
1 |
Covered |
T1,T2,T13 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T13 |
0 |
0 |
1 |
Covered |
T1,T2,T13 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
124417 |
0 |
0 |
T1 |
48761 |
750 |
0 |
0 |
T2 |
51138 |
843 |
0 |
0 |
T10 |
0 |
1541 |
0 |
0 |
T11 |
0 |
1662 |
0 |
0 |
T13 |
0 |
762 |
0 |
0 |
T14 |
0 |
938 |
0 |
0 |
T62 |
0 |
794 |
0 |
0 |
T99 |
0 |
769 |
0 |
0 |
T100 |
37696 |
0 |
0 |
0 |
T101 |
86343 |
0 |
0 |
0 |
T102 |
231334 |
0 |
0 |
0 |
T103 |
84111 |
0 |
0 |
0 |
T104 |
73381 |
0 |
0 |
0 |
T105 |
491102 |
0 |
0 |
0 |
T106 |
41826 |
0 |
0 |
0 |
T107 |
296275 |
0 |
0 |
0 |
T413 |
0 |
603 |
0 |
0 |
T414 |
0 |
1431 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
314 |
0 |
0 |
T1 |
48761 |
2 |
0 |
0 |
T2 |
51138 |
2 |
0 |
0 |
T10 |
0 |
4 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T62 |
0 |
2 |
0 |
0 |
T99 |
0 |
2 |
0 |
0 |
T100 |
37696 |
0 |
0 |
0 |
T101 |
86343 |
0 |
0 |
0 |
T102 |
231334 |
0 |
0 |
0 |
T103 |
84111 |
0 |
0 |
0 |
T104 |
73381 |
0 |
0 |
0 |
T105 |
491102 |
0 |
0 |
0 |
T106 |
41826 |
0 |
0 |
0 |
T107 |
296275 |
0 |
0 |
0 |
T413 |
0 |
2 |
0 |
0 |
T414 |
0 |
4 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
0 |
1 |
156 |
0 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T441 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T9,T148,T149 |
1 | - | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
106214 |
0 |
0 |
T9 |
404309 |
255 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
4018 |
0 |
0 |
T149 |
0 |
464 |
0 |
0 |
T150 |
0 |
1447 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
1028 |
0 |
0 |
T393 |
0 |
3624 |
0 |
0 |
T394 |
0 |
2924 |
0 |
0 |
T395 |
0 |
989 |
0 |
0 |
T415 |
0 |
470 |
0 |
0 |
T416 |
0 |
275 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
269 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
10 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
3 |
0 |
0 |
T393 |
0 |
9 |
0 |
0 |
T394 |
0 |
8 |
0 |
0 |
T395 |
0 |
3 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
0 |
1 |
156 |
0 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T442 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T9,T148,T149 |
1 | - | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
115055 |
0 |
0 |
T9 |
404309 |
282 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
7032 |
0 |
0 |
T149 |
0 |
463 |
0 |
0 |
T150 |
0 |
4939 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
3706 |
0 |
0 |
T393 |
0 |
347 |
0 |
0 |
T394 |
0 |
2881 |
0 |
0 |
T395 |
0 |
2684 |
0 |
0 |
T415 |
0 |
475 |
0 |
0 |
T416 |
0 |
269 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
288 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
18 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
12 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
10 |
0 |
0 |
T393 |
0 |
1 |
0 |
0 |
T394 |
0 |
8 |
0 |
0 |
T395 |
0 |
7 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T15,T9 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T3,T15,T9 |
1 | 1 | Covered | T3,T15,T9 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T15,T9 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T15,T9 |
1 | 1 | Covered | T3,T15,T9 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T3,T15,T9 |
0 |
0 |
1 |
Covered |
T3,T15,T9 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T3,T15,T9 |
0 |
0 |
1 |
Covered |
T3,T15,T9 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
117854 |
0 |
0 |
T3 |
44995 |
398 |
0 |
0 |
T9 |
0 |
321 |
0 |
0 |
T15 |
0 |
419 |
0 |
0 |
T16 |
0 |
385 |
0 |
0 |
T148 |
0 |
3987 |
0 |
0 |
T149 |
0 |
370 |
0 |
0 |
T150 |
0 |
4061 |
0 |
0 |
T392 |
0 |
2564 |
0 |
0 |
T393 |
0 |
2800 |
0 |
0 |
T394 |
0 |
718 |
0 |
0 |
T417 |
103743 |
0 |
0 |
0 |
T418 |
24504 |
0 |
0 |
0 |
T419 |
83196 |
0 |
0 |
0 |
T420 |
64693 |
0 |
0 |
0 |
T421 |
70746 |
0 |
0 |
0 |
T422 |
147025 |
0 |
0 |
0 |
T423 |
97972 |
0 |
0 |
0 |
T424 |
64543 |
0 |
0 |
0 |
T425 |
17821 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
295 |
0 |
0 |
T3 |
44995 |
1 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T148 |
0 |
10 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
10 |
0 |
0 |
T392 |
0 |
7 |
0 |
0 |
T393 |
0 |
7 |
0 |
0 |
T394 |
0 |
2 |
0 |
0 |
T417 |
103743 |
0 |
0 |
0 |
T418 |
24504 |
0 |
0 |
0 |
T419 |
83196 |
0 |
0 |
0 |
T420 |
64693 |
0 |
0 |
0 |
T421 |
70746 |
0 |
0 |
0 |
T422 |
147025 |
0 |
0 |
0 |
T423 |
97972 |
0 |
0 |
0 |
T424 |
64543 |
0 |
0 |
0 |
T425 |
17821 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
95941 |
0 |
0 |
T9 |
404309 |
322 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
1509 |
0 |
0 |
T149 |
0 |
379 |
0 |
0 |
T150 |
0 |
263 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
626 |
0 |
0 |
T393 |
0 |
1651 |
0 |
0 |
T394 |
0 |
1360 |
0 |
0 |
T395 |
0 |
1311 |
0 |
0 |
T415 |
0 |
439 |
0 |
0 |
T416 |
0 |
290 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
245 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
4 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
1 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T393 |
0 |
4 |
0 |
0 |
T394 |
0 |
4 |
0 |
0 |
T395 |
0 |
4 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T443 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
108896 |
0 |
0 |
T9 |
404309 |
304 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
7920 |
0 |
0 |
T149 |
0 |
425 |
0 |
0 |
T150 |
0 |
1178 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
977 |
0 |
0 |
T393 |
0 |
4030 |
0 |
0 |
T394 |
0 |
1013 |
0 |
0 |
T395 |
0 |
3627 |
0 |
0 |
T415 |
0 |
479 |
0 |
0 |
T416 |
0 |
323 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
275 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
20 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
3 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
3 |
0 |
0 |
T393 |
0 |
10 |
0 |
0 |
T394 |
0 |
3 |
0 |
0 |
T395 |
0 |
9 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T12,T9,T148 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T12,T9,T148 |
1 | 1 | Covered | T12,T9,T148 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T12,T9,T148 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T12,T9,T148 |
1 | 1 | Covered | T12,T9,T148 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T12,T9,T148 |
0 |
0 |
1 |
Covered |
T12,T9,T148 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T12,T9,T148 |
0 |
0 |
1 |
Covered |
T12,T9,T148 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
115827 |
0 |
0 |
T9 |
0 |
256 |
0 |
0 |
T12 |
19498 |
330 |
0 |
0 |
T88 |
58303 |
0 |
0 |
0 |
T148 |
0 |
2875 |
0 |
0 |
T149 |
0 |
400 |
0 |
0 |
T150 |
0 |
3221 |
0 |
0 |
T392 |
0 |
2891 |
0 |
0 |
T393 |
0 |
2001 |
0 |
0 |
T394 |
0 |
2440 |
0 |
0 |
T395 |
0 |
2360 |
0 |
0 |
T415 |
0 |
368 |
0 |
0 |
T433 |
25867 |
0 |
0 |
0 |
T434 |
18101 |
0 |
0 |
0 |
T435 |
55109 |
0 |
0 |
0 |
T436 |
400702 |
0 |
0 |
0 |
T437 |
39685 |
0 |
0 |
0 |
T438 |
549898 |
0 |
0 |
0 |
T439 |
152632 |
0 |
0 |
0 |
T440 |
27790 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
292 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T12 |
19498 |
1 |
0 |
0 |
T88 |
58303 |
0 |
0 |
0 |
T148 |
0 |
7 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
8 |
0 |
0 |
T392 |
0 |
8 |
0 |
0 |
T393 |
0 |
5 |
0 |
0 |
T394 |
0 |
7 |
0 |
0 |
T395 |
0 |
6 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T433 |
25867 |
0 |
0 |
0 |
T434 |
18101 |
0 |
0 |
0 |
T435 |
55109 |
0 |
0 |
0 |
T436 |
400702 |
0 |
0 |
0 |
T437 |
39685 |
0 |
0 |
0 |
T438 |
549898 |
0 |
0 |
0 |
T439 |
152632 |
0 |
0 |
0 |
T440 |
27790 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T444,T148 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
109064 |
0 |
0 |
T9 |
404309 |
269 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
6331 |
0 |
0 |
T149 |
0 |
364 |
0 |
0 |
T150 |
0 |
737 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
642 |
0 |
0 |
T393 |
0 |
1574 |
0 |
0 |
T394 |
0 |
699 |
0 |
0 |
T395 |
0 |
2647 |
0 |
0 |
T415 |
0 |
477 |
0 |
0 |
T416 |
0 |
304 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
275 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
16 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T393 |
0 |
4 |
0 |
0 |
T394 |
0 |
2 |
0 |
0 |
T395 |
0 |
7 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T13 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Covered | T1,T2,T13 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T13 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T13 |
1 | 1 | Covered | T1,T2,T13 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T13 |
0 |
0 |
1 |
Covered |
T1,T2,T13 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T13 |
0 |
0 |
1 |
Covered |
T1,T2,T13 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
103939 |
0 |
0 |
T1 |
48761 |
253 |
0 |
0 |
T2 |
51138 |
468 |
0 |
0 |
T10 |
0 |
673 |
0 |
0 |
T11 |
0 |
795 |
0 |
0 |
T13 |
0 |
266 |
0 |
0 |
T14 |
0 |
400 |
0 |
0 |
T62 |
0 |
254 |
0 |
0 |
T99 |
0 |
272 |
0 |
0 |
T100 |
37696 |
0 |
0 |
0 |
T101 |
86343 |
0 |
0 |
0 |
T102 |
231334 |
0 |
0 |
0 |
T103 |
84111 |
0 |
0 |
0 |
T104 |
73381 |
0 |
0 |
0 |
T105 |
491102 |
0 |
0 |
0 |
T106 |
41826 |
0 |
0 |
0 |
T107 |
296275 |
0 |
0 |
0 |
T413 |
0 |
349 |
0 |
0 |
T414 |
0 |
685 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
264 |
0 |
0 |
T1 |
48761 |
1 |
0 |
0 |
T2 |
51138 |
1 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T62 |
0 |
1 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
T100 |
37696 |
0 |
0 |
0 |
T101 |
86343 |
0 |
0 |
0 |
T102 |
231334 |
0 |
0 |
0 |
T103 |
84111 |
0 |
0 |
0 |
T104 |
73381 |
0 |
0 |
0 |
T105 |
491102 |
0 |
0 |
0 |
T106 |
41826 |
0 |
0 |
0 |
T107 |
296275 |
0 |
0 |
0 |
T413 |
0 |
1 |
0 |
0 |
T414 |
0 |
2 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T441 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
101080 |
0 |
0 |
T9 |
404309 |
255 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
3197 |
0 |
0 |
T149 |
0 |
372 |
0 |
0 |
T150 |
0 |
2844 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
1334 |
0 |
0 |
T393 |
0 |
2754 |
0 |
0 |
T394 |
0 |
2112 |
0 |
0 |
T395 |
0 |
4014 |
0 |
0 |
T415 |
0 |
434 |
0 |
0 |
T416 |
0 |
308 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
253 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
8 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
7 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
4 |
0 |
0 |
T393 |
0 |
7 |
0 |
0 |
T394 |
0 |
6 |
0 |
0 |
T395 |
0 |
10 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T445 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
125158 |
0 |
0 |
T9 |
404309 |
318 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
5869 |
0 |
0 |
T149 |
0 |
449 |
0 |
0 |
T150 |
0 |
3779 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
1427 |
0 |
0 |
T393 |
0 |
2361 |
0 |
0 |
T394 |
0 |
4679 |
0 |
0 |
T395 |
0 |
2333 |
0 |
0 |
T415 |
0 |
396 |
0 |
0 |
T416 |
0 |
293 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
313 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
15 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
9 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
4 |
0 |
0 |
T393 |
0 |
6 |
0 |
0 |
T394 |
0 |
13 |
0 |
0 |
T395 |
0 |
6 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T446,T148 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T148,T149 |
1 | 1 | Covered | T9,T148,T149 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T9,T148,T149 |
0 |
0 |
1 |
Covered |
T9,T148,T149 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
114194 |
0 |
0 |
T9 |
404309 |
350 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
6447 |
0 |
0 |
T149 |
0 |
430 |
0 |
0 |
T150 |
0 |
4897 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
1855 |
0 |
0 |
T393 |
0 |
1593 |
0 |
0 |
T394 |
0 |
3616 |
0 |
0 |
T395 |
0 |
1332 |
0 |
0 |
T415 |
0 |
436 |
0 |
0 |
T416 |
0 |
316 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
287 |
0 |
0 |
T9 |
404309 |
1 |
0 |
0 |
T90 |
70993 |
0 |
0 |
0 |
T148 |
0 |
16 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
12 |
0 |
0 |
T159 |
42644 |
0 |
0 |
0 |
T324 |
43192 |
0 |
0 |
0 |
T333 |
24063 |
0 |
0 |
0 |
T392 |
0 |
5 |
0 |
0 |
T393 |
0 |
4 |
0 |
0 |
T394 |
0 |
10 |
0 |
0 |
T395 |
0 |
4 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T416 |
0 |
1 |
0 |
0 |
T427 |
24493 |
0 |
0 |
0 |
T428 |
26796 |
0 |
0 |
0 |
T429 |
19201 |
0 |
0 |
0 |
T430 |
105867 |
0 |
0 |
0 |
T431 |
46760 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T412,T8 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T412,T8 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T7,T412,T8 |
1 | 1 | Covered | T7,T8,T9 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T7,T412,T8 |
0 |
0 |
1 |
Covered |
T7,T8,T9 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T7,T412,T8 |
0 |
0 |
1 |
Covered |
T7,T8,T9 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
105608 |
0 |
0 |
T7 |
33435 |
243 |
0 |
0 |
T8 |
0 |
310 |
0 |
0 |
T9 |
0 |
272 |
0 |
0 |
T148 |
0 |
7080 |
0 |
0 |
T149 |
0 |
395 |
0 |
0 |
T150 |
0 |
1942 |
0 |
0 |
T238 |
102906 |
0 |
0 |
0 |
T274 |
20231 |
0 |
0 |
0 |
T290 |
68959 |
0 |
0 |
0 |
T372 |
46510 |
0 |
0 |
0 |
T392 |
0 |
1772 |
0 |
0 |
T393 |
0 |
250 |
0 |
0 |
T394 |
0 |
685 |
0 |
0 |
T412 |
0 |
362 |
0 |
0 |
T447 |
57788 |
0 |
0 |
0 |
T448 |
22850 |
0 |
0 |
0 |
T449 |
37231 |
0 |
0 |
0 |
T450 |
49800 |
0 |
0 |
0 |
T451 |
236918 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1792917 |
1576102 |
0 |
0 |
T4 |
4791 |
4619 |
0 |
0 |
T5 |
998 |
826 |
0 |
0 |
T6 |
1009 |
836 |
0 |
0 |
T17 |
4245 |
4012 |
0 |
0 |
T18 |
779 |
483 |
0 |
0 |
T19 |
3371 |
3135 |
0 |
0 |
T42 |
855 |
681 |
0 |
0 |
T53 |
4365 |
4191 |
0 |
0 |
T54 |
2709 |
2536 |
0 |
0 |
T86 |
389 |
215 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
266 |
0 |
0 |
T7 |
33435 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T148 |
0 |
18 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T238 |
102906 |
0 |
0 |
0 |
T274 |
20231 |
0 |
0 |
0 |
T290 |
68959 |
0 |
0 |
0 |
T372 |
46510 |
0 |
0 |
0 |
T392 |
0 |
5 |
0 |
0 |
T393 |
0 |
1 |
0 |
0 |
T394 |
0 |
2 |
0 |
0 |
T395 |
0 |
3 |
0 |
0 |
T447 |
57788 |
0 |
0 |
0 |
T448 |
22850 |
0 |
0 |
0 |
T449 |
37231 |
0 |
0 |
0 |
T450 |
49800 |
0 |
0 |
0 |
T451 |
236918 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145465172 |
144697391 |
0 |
0 |
T4 |
548413 |
547869 |
0 |
0 |
T5 |
59942 |
59651 |
0 |
0 |
T6 |
98609 |
97979 |
0 |
0 |
T17 |
476582 |
475585 |
0 |
0 |
T18 |
53201 |
51037 |
0 |
0 |
T19 |
368689 |
367849 |
0 |
0 |
T42 |
66411 |
65922 |
0 |
0 |
T53 |
492616 |
492179 |
0 |
0 |
T54 |
292999 |
292646 |
0 |
0 |
T86 |
25377 |
24581 |
0 |
0 |