Unified Coverage Report :: Module :: chip_earlgrey_asic

Module : chip_earlgrey_asic

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.90	80.00	100.00	95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.83	80.00	100.00	98.48

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.83	80.00	100.00	98.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.35	95.48	94.18	95.43		94.99	96.65

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
top_earlgrey	95.32	95.41	93.73	95.43		94.80	97.23
u_ast	93.28			93.28
u_padring	97.80	99.21	99.81	96.57		99.60	93.81
u_prim_usb_diff_rx	96.30	100.00	88.89			100.00

Line Coverage for Module : chip_earlgrey_asic

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	789	1	0	0.00
CONT_ASSIGN	802	1	0	0.00
CONT_ASSIGN	831	1	0	0.00
CONT_ASSIGN	838	1	0	0.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	860	1	0	0.00
CONT_ASSIGN	863	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1031	1	1	100.00
CONT_ASSIGN	1038	1	1	100.00
CONT_ASSIGN	1055	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00
CONT_ASSIGN	1057	1	1	100.00
CONT_ASSIGN	1058	1	1	100.00
CONT_ASSIGN	1062	1	1	100.00
CONT_ASSIGN	1063	1	1	100.00
CONT_ASSIGN	1064	1	1	100.00
CONT_ASSIGN	1065	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
214	1	1
215	1	1
789	0	1
802	0	1
831	0	1
838	0	1
845	1	1
848	1	1
854	1	1
856	1	1
860	0	1
863	1	1
1028	1	1
1029	1	1
1030	1	1
1031	1	1
1038	1	1
1055	1	1
1056	1	1
1057	1	1
1058	1	1
1062	1	1
1063	1	1
1064	1	1
1065	1	1

---

Cond Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T248,T125,T126

---

Toggle Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Totals	70	64	91.43
Total Bits	140	134	95.71
Total Bits 0->1	70	70	100.00
Total Bits 1->0	70	64	91.43

Ports	70	64	91.43
Port Bits	140	134	95.71
Port Bits 0->1	70	70	100.00
Port Bits 1->0	70	64	91.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
POR_N	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INOUT
USB_P	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INOUT
USB_N	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INOUT
CC1	No	No		Yes	T20,T21,T22	INOUT
CC2	No	No		Yes	T20,T21,T22	INOUT
FLASH_TEST_VOLT	No	No		Yes	T20,T21,T22	INOUT
FLASH_TEST_MODE0	No	No		Yes	T20,T21,T22	INOUT
FLASH_TEST_MODE1	No	No		Yes	T20,T21,T22	INOUT
OTP_EXT_VOLT	No	No		Yes	T20,T21,T22	INOUT
SPI_HOST_D0	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INOUT
SPI_HOST_D1	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INOUT
SPI_HOST_D2	Yes	Yes	T23,T189,T191	Yes	T23,T189,T20	INOUT
SPI_HOST_D3	Yes	Yes	T23,T189,T191	Yes	T23,T189,T191	INOUT
SPI_HOST_CLK	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INOUT
SPI_HOST_CS_L	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INOUT
SPI_DEV_D0	Yes	Yes	T23,T147,T49	Yes	T23,T147,T49	INOUT
SPI_DEV_D1	Yes	Yes	T23,T147,T49	Yes	T23,T147,T49	INOUT
SPI_DEV_D2	Yes	Yes	T23,T189,T191	Yes	T23,T189,T21	INOUT
SPI_DEV_D3	Yes	Yes	T23,T189,T191	Yes	T23,T189,T20	INOUT
SPI_DEV_CLK	Yes	Yes	T23,T147,T49	Yes	T23,T147,T49	INOUT
SPI_DEV_CS_L	Yes	Yes	T23,T147,T210	Yes	T23,T147,T210	INOUT
IOR8	Yes	Yes	T32,T202,T33	Yes	T32,T202,T33	INOUT
IOR9	Yes	Yes	T32,T33,T34	Yes	T46,T32,T202	INOUT
IOA0	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INOUT
IOA1	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INOUT
IOA2	Yes	Yes	T27,T108,T151	Yes	T27,T108,T151	INOUT
IOA3	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOA4	Yes	Yes	T27,T147,T122	Yes	T27,T147,T122	INOUT
IOA5	Yes	Yes	T27,T147,T122	Yes	T27,T147,T122	INOUT
IOA6	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOA7	Yes	Yes	T27,T49,T36	Yes	T27,T49,T36	INOUT
IOA8	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOB0	Yes	Yes	T43,T44,T39	Yes	T43,T44,T39	INOUT
IOB1	Yes	Yes	T43,T44,T39	Yes	T43,T44,T21	INOUT
IOB2	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INOUT
IOB3	Yes	Yes	T43,T32,T202	Yes	T43,T202,T33	INOUT
IOB4	Yes	Yes	T43,T211,T212	Yes	T43,T211,T212	INOUT
IOB5	Yes	Yes	T211,T212,T375	Yes	T211,T212,T375	INOUT
IOB6	Yes	Yes	T27,T32,T202	Yes	T27,T202,T36	INOUT
IOB7	Yes	Yes	T27,T1,T2	Yes	T27,T46,T1	INOUT
IOB8	Yes	Yes	T27,T202,T36	Yes	T27,T202,T36	INOUT
IOB9	Yes	Yes	T213,T27,T32	Yes	T213,T27,T32	INOUT
IOB10	Yes	Yes	T213,T27,T108	Yes	T213,T27,T108	INOUT
IOB11	Yes	Yes	T213,T27,T108	Yes	T213,T27,T108	INOUT
IOB12	Yes	Yes	T213,T27,T108	Yes	T213,T27,T108	INOUT
IOC0	Yes	Yes	T17,T53,T54	Yes	T176,T214,T379	INOUT
IOC1	Yes	Yes	T147,T210,T214	Yes	T214,T379,T153	INOUT
IOC2	Yes	Yes	T147,T210,T214	Yes	T214,T379,T153	INOUT
IOC3	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	INOUT
IOC4	Yes	Yes	T17,T19,T68	Yes	T17,T19,T68	INOUT
IOC5	Yes	Yes	T71,T72,T219	Yes	T72,T219,T65	INOUT
IOC6	Yes	Yes	T18,T57,T118	Yes	T18,T57,T118	INOUT
IOC7	Yes	Yes	T202,T33,T34	Yes	T29,T30,T32	INOUT
IOC8	Yes	Yes	T71,T72,T219	Yes	T72,T219,T65	INOUT
IOC9	Yes	Yes	T27,T202,T36	Yes	T27,T46,T32	INOUT
IOC10	Yes	Yes	T27,T108,T218	Yes	T27,T108,T218	INOUT
IOC11	Yes	Yes	T27,T108,T218	Yes	T27,T108,T218	INOUT
IOC12	Yes	Yes	T27,T108,T218	Yes	T27,T108,T218	INOUT
IOR0	Yes	Yes	T18,T57,T58	Yes	T18,T57,T58	INOUT
IOR1	Yes	Yes	T18,T57,T58	Yes	T18,T57,T58	INOUT
IOR2	Yes	Yes	T18,T57,T58	Yes	T18,T57,T58	INOUT
IOR3	Yes	Yes	T18,T57,T58	Yes	T18,T57,T58	INOUT
IOR4	Yes	Yes	T18,T55,T56	Yes	T18,T57,T58	INOUT
IOR5	Yes	Yes	T27,T32,T36	Yes	T27,T32,T36	INOUT
IOR6	Yes	Yes	T27,T36,T37	Yes	T27,T32,T36	INOUT
IOR7	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOR10	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOR11	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOR12	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOR13	Yes	Yes	T27,T1,T2	Yes	T27,T1,T2	INOUT

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	789	1	0	0.00
CONT_ASSIGN	802	1	0	0.00
CONT_ASSIGN	831	1	0	0.00
CONT_ASSIGN	838	1	0	0.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	860	1	0	0.00
CONT_ASSIGN	863	1	1	100.00
CONT_ASSIGN	1028	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1031	1	1	100.00
CONT_ASSIGN	1038	1	1	100.00
CONT_ASSIGN	1055	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00
CONT_ASSIGN	1057	1	1	100.00
CONT_ASSIGN	1058	1	1	100.00
CONT_ASSIGN	1062	1	1	100.00
CONT_ASSIGN	1063	1	1	100.00
CONT_ASSIGN	1064	1	1	100.00
CONT_ASSIGN	1065	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
214	1	1
215	1	1
789	0	1
802	0	1
831	0	1
838	0	1
845	1	1
848	1	1
854	1	1
856	1	1
860	0	1
863	1	1
1028	1	1
1029	1	1
1030	1	1
1031	1	1
1038	1	1
1055	1	1
1056	1	1
1057	1	1
1058	1	1
1062	1	1
1063	1	1
1064	1	1
1065	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T248,T125,T126

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	66	64	96.97
Total Bits	132	130	98.48
Total Bits 0->1	66	66	100.00
Total Bits 1->0	66	64	96.97

Ports	66	64	96.97
Port Bits	132	130	98.48
Port Bits 0->1	66	66	100.00
Port Bits 1->0	66	64	96.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
POR_N	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INOUT
USB_P	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INOUT
USB_N	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INOUT
CC1	No	No		Yes	T20,T21,T22	INOUT
CC2	No	No		Yes	T20,T21,T22	INOUT
FLASH_TEST_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INOUT
SPI_HOST_D1	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INOUT
SPI_HOST_D2	Yes	Yes	T23,T189,T191	Yes	T23,T189,T20	INOUT
SPI_HOST_D3	Yes	Yes	T23,T189,T191	Yes	T23,T189,T191	INOUT
SPI_HOST_CLK	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INOUT
SPI_HOST_CS_L	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INOUT
SPI_DEV_D0	Yes	Yes	T23,T147,T49	Yes	T23,T147,T49	INOUT
SPI_DEV_D1	Yes	Yes	T23,T147,T49	Yes	T23,T147,T49	INOUT
SPI_DEV_D2	Yes	Yes	T23,T189,T191	Yes	T23,T189,T21	INOUT
SPI_DEV_D3	Yes	Yes	T23,T189,T191	Yes	T23,T189,T20	INOUT
SPI_DEV_CLK	Yes	Yes	T23,T147,T49	Yes	T23,T147,T49	INOUT
SPI_DEV_CS_L	Yes	Yes	T23,T147,T210	Yes	T23,T147,T210	INOUT
IOR8	Yes	Yes	T32,T202,T33	Yes	T32,T202,T33	INOUT
IOR9	Yes	Yes	T32,T33,T34	Yes	T46,T32,T202	INOUT
IOA0	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INOUT
IOA1	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INOUT
IOA2	Yes	Yes	T27,T108,T151	Yes	T27,T108,T151	INOUT
IOA3	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOA4	Yes	Yes	T27,T147,T122	Yes	T27,T147,T122	INOUT
IOA5	Yes	Yes	T27,T147,T122	Yes	T27,T147,T122	INOUT
IOA6	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOA7	Yes	Yes	T27,T49,T36	Yes	T27,T49,T36	INOUT
IOA8	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOB0	Yes	Yes	T43,T44,T39	Yes	T43,T44,T39	INOUT
IOB1	Yes	Yes	T43,T44,T39	Yes	T43,T44,T21	INOUT
IOB2	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INOUT
IOB3	Yes	Yes	T43,T32,T202	Yes	T43,T202,T33	INOUT
IOB4	Yes	Yes	T43,T211,T212	Yes	T43,T211,T212	INOUT
IOB5	Yes	Yes	T211,T212,T375	Yes	T211,T212,T375	INOUT
IOB6	Yes	Yes	T27,T32,T202	Yes	T27,T202,T36	INOUT
IOB7	Yes	Yes	T27,T1,T2	Yes	T27,T46,T1	INOUT
IOB8	Yes	Yes	T27,T202,T36	Yes	T27,T202,T36	INOUT
IOB9	Yes	Yes	T213,T27,T32	Yes	T213,T27,T32	INOUT
IOB10	Yes	Yes	T213,T27,T108	Yes	T213,T27,T108	INOUT
IOB11	Yes	Yes	T213,T27,T108	Yes	T213,T27,T108	INOUT
IOB12	Yes	Yes	T213,T27,T108	Yes	T213,T27,T108	INOUT
IOC0	Yes	Yes	T17,T53,T54	Yes	T176,T214,T379	INOUT
IOC1	Yes	Yes	T147,T210,T214	Yes	T214,T379,T153	INOUT
IOC2	Yes	Yes	T147,T210,T214	Yes	T214,T379,T153	INOUT
IOC3	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	INOUT
IOC4	Yes	Yes	T17,T19,T68	Yes	T17,T19,T68	INOUT
IOC5	Yes	Yes	T71,T72,T219	Yes	T72,T219,T65	INOUT
IOC6	Yes	Yes	T18,T57,T118	Yes	T18,T57,T118	INOUT
IOC7	Yes	Yes	T202,T33,T34	Yes	T29,T30,T32	INOUT
IOC8	Yes	Yes	T71,T72,T219	Yes	T72,T219,T65	INOUT
IOC9	Yes	Yes	T27,T202,T36	Yes	T27,T46,T32	INOUT
IOC10	Yes	Yes	T27,T108,T218	Yes	T27,T108,T218	INOUT
IOC11	Yes	Yes	T27,T108,T218	Yes	T27,T108,T218	INOUT
IOC12	Yes	Yes	T27,T108,T218	Yes	T27,T108,T218	INOUT
IOR0	Yes	Yes	T18,T57,T58	Yes	T18,T57,T58	INOUT
IOR1	Yes	Yes	T18,T57,T58	Yes	T18,T57,T58	INOUT
IOR2	Yes	Yes	T18,T57,T58	Yes	T18,T57,T58	INOUT
IOR3	Yes	Yes	T18,T57,T58	Yes	T18,T57,T58	INOUT
IOR4	Yes	Yes	T18,T55,T56	Yes	T18,T57,T58	INOUT
IOR5	Yes	Yes	T27,T32,T36	Yes	T27,T32,T36	INOUT
IOR6	Yes	Yes	T27,T36,T37	Yes	T27,T32,T36	INOUT
IOR7	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOR10	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOR11	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOR12	Yes	Yes	T27,T36,T37	Yes	T27,T36,T37	INOUT
IOR13	Yes	Yes	T27,T1,T2	Yes	T27,T1,T2	INOUT