Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3515311	1			T75	1743		T76	19		T77	136
values[2]	723077	1			T76	18		T77	51		T79	604
values[3]	102092	1			T76	18		T79	250		T492	19
values[4]	54333	1			T76	18		T79	6		T401	6
values[5]	35827	1			T76	18		T387	96		T509	16
values[6]	26718	1			T76	18		T387	108		T509	16
values[7]	21551	1			T76	18		T387	110		T509	16
values[8]	18267	1			T76	18		T387	103		T509	16
values[9]	15877	1			T76	18		T387	94		T509	16
values[10]	14402	1			T76	18		T387	61		T509	16
values[11]	13525	1			T76	18		T387	55		T509	16
values[12]	12841	1			T76	18		T387	47		T509	16
values[13]	11994	1			T76	19		T387	39		T509	16
values[14]	11025	1			T76	18		T387	55		T509	16
values[15]	10509	1			T76	19		T387	67		T509	16
values[16]	10040	1			T76	18		T387	64		T509	16
values[17]	9811	1			T76	18		T387	57		T509	17
values[18]	9591	1			T76	18		T387	81		T509	16
values[19]	9114	1			T76	18		T387	73		T509	17
values[20]	9052	1			T76	18		T387	71		T509	16
values[21]	8532	1			T76	18		T387	75		T509	16
values[22]	8276	1			T76	18		T387	71		T509	16
values[23]	8167	1			T76	18		T387	96		T509	16
values[24]	7829	1			T76	18		T387	69		T509	16
values[25]	7381	1			T76	18		T387	53		T509	16
values[26]	6969	1			T76	19		T387	58		T509	16
values[27]	6845	1			T76	18		T387	58		T509	17
values[28]	6757	1			T76	18		T387	65		T509	16
values[29]	6357	1			T76	19		T387	54		T509	16
values[30]	5956	1			T76	19		T387	41		T509	16
values[31]	5402	1			T76	18		T387	54		T509	16
values[32]	5147	1			T76	18		T387	52		T509	16
values[33]	4715	1			T76	18		T387	27		T509	16
values[34]	4384	1			T76	18		T387	24		T509	16
values[35]	4172	1			T76	18		T387	17		T509	16
values[36]	3920	1			T76	18		T387	22		T509	16
values[37]	3678	1			T76	18		T387	19		T509	16
values[38]	3603	1			T76	18		T387	16		T509	16
values[39]	3612	1			T76	18		T387	17		T509	18
values[40]	3480	1			T76	18		T387	20		T509	16
values[41]	3297	1			T76	18		T387	16		T509	16
values[42]	3397	1			T76	18		T387	8		T509	16
values[43]	3241	1			T76	19		T387	14		T509	16
values[44]	3168	1			T76	18		T387	13		T509	16
values[45]	3039	1			T76	19		T387	17		T509	16
values[46]	3010	1			T76	19		T387	15		T509	16
values[47]	3078	1			T76	19		T387	17		T509	16
values[48]	3080	1			T76	18		T387	14		T509	17
values[49]	3096	1			T76	18		T387	11		T509	16
values[50]	2943	1			T76	18		T387	12		T509	16
values[51]	2891	1			T76	19		T387	8		T509	16
values[52]	2779	1			T76	18		T387	12		T509	16
values[53]	2750	1			T76	18		T387	13		T509	16
values[54]	2664	1			T76	19		T387	6		T509	16
values[55]	2633	1			T76	18		T387	7		T509	17
values[56]	2631	1			T76	19		T387	7		T509	17
values[57]	2504	1			T76	18		T387	6		T509	16
values[58]	2385	1			T76	18		T387	3		T509	16
values[59]	2361	1			T76	18		T509	16		T470	1
values[60]	2429	1			T76	18		T509	17		T470	3
values[61]	2836	1			T76	18		T509	16		T470	2
values[62]	4449	1			T76	18		T509	16		T470	10
values[63]	17510	1			T76	18		T509	16		T470	19
values[64]	226247	1			T76	3325		T509	3137		T470	107

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4538234	1			T75	1798		T76	2106		T77	119
values[2]	762372	1			T76	639		T77	26		T79	550
values[3]	75972	1			T76	188		T77	6		T79	162
values[4]	13578	1			T76	55		T79	56		T492	4
values[5]	5141	1			T76	19		T79	25		T492	3
values[6]	3164	1			T76	8		T79	7		T492	1
values[7]	2364	1			T76	5		T79	2		T509	5
values[8]	2107	1			T76	4		T509	5		T516	2
values[9]	1847	1			T76	4		T509	3		T785	2
values[10]	1712	1			T76	4		T509	3		T785	2
values[11]	1578	1			T76	5		T509	3		T785	1
values[12]	1435	1			T76	4		T509	3		T785	2
values[13]	1335	1			T76	4		T509	3		T785	1
values[14]	1253	1			T76	4		T509	3		T785	2
values[15]	1227	1			T76	4		T509	3		T785	2
values[16]	1129	1			T76	4		T509	3		T785	1
values[17]	1040	1			T76	4		T509	3		T785	1
values[18]	1053	1			T76	4		T509	3		T785	1
values[19]	951	1			T76	4		T509	3		T785	1
values[20]	869	1			T76	4		T509	3		T785	2
values[21]	910	1			T76	4		T509	3		T785	1
values[22]	950	1			T76	4		T509	3		T785	2
values[23]	876	1			T76	4		T509	3		T785	1
values[24]	786	1			T76	4		T509	3		T785	1
values[25]	707	1			T76	4		T509	3		T785	3
values[26]	685	1			T76	4		T509	3		T785	2
values[27]	671	1			T76	4		T509	3		T785	1
values[28]	670	1			T76	4		T509	3		T785	1
values[29]	657	1			T76	4		T509	3		T785	2
values[30]	609	1			T76	4		T509	3		T785	1
values[31]	572	1			T76	4		T509	3		T785	1
values[32]	583	1			T76	4		T509	3		T785	1
values[33]	570	1			T76	4		T509	3		T785	3
values[34]	554	1			T76	4		T509	3		T785	3
values[35]	541	1			T76	4		T509	3		T785	4
values[36]	531	1			T76	4		T509	3		T785	2
values[37]	499	1			T76	4		T509	3		T785	1
values[38]	484	1			T76	4		T509	3		T785	1
values[39]	498	1			T76	4		T509	3		T785	1
values[40]	486	1			T76	4		T509	4		T785	1
values[41]	466	1			T76	4		T509	3		T785	1
values[42]	434	1			T76	4		T509	3		T785	5
values[43]	482	1			T76	4		T509	3		T785	2
values[44]	450	1			T76	4		T509	3		T785	5
values[45]	455	1			T76	4		T509	3		T785	2
values[46]	461	1			T76	4		T509	3		T785	3
values[47]	443	1			T76	4		T509	3		T785	2
values[48]	392	1			T76	4		T509	3		T785	3
values[49]	422	1			T76	4		T509	3		T785	2
values[50]	399	1			T76	4		T509	3		T785	3
values[51]	390	1			T76	4		T509	3		T785	3
values[52]	385	1			T76	4		T509	3		T785	1
values[53]	386	1			T76	4		T509	3		T785	3
values[54]	374	1			T76	4		T509	3		T785	2
values[55]	357	1			T76	4		T509	4		T785	5
values[56]	364	1			T76	4		T509	3		T785	5
values[57]	341	1			T76	4		T509	3		T785	3
values[58]	369	1			T76	4		T509	3		T785	2
values[59]	333	1			T76	4		T509	3		T785	1
values[60]	327	1			T76	4		T509	3		T785	1
values[61]	346	1			T76	5		T509	3		T785	3
values[62]	610	1			T76	4		T509	3		T785	3
values[63]	2866	1			T76	5		T509	3		T785	30
values[64]	25502	1			T76	873		T509	533		T785	130

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	565809	1			T75	1798		T76	19		T77	1
values[2]	2517972	1			T76	18		T77	119		T79	1913
values[3]	1090054	1			T76	19		T77	42		T79	690
values[4]	144156	1			T76	18		T79	24		T492	2
values[5]	75321	1			T76	18		T79	2		T401	80
values[6]	48716	1			T76	18		T401	45		T387	90
values[7]	34841	1			T76	18		T401	37		T387	68
values[8]	27414	1			T76	18		T401	29		T387	71
values[9]	22446	1			T76	18		T401	8		T387	46
values[10]	19474	1			T76	18		T401	12		T387	47
values[11]	17539	1			T76	18		T401	4		T387	63
values[12]	16298	1			T76	18		T401	13		T387	93
values[13]	15155	1			T76	18		T401	13		T387	105
values[14]	13951	1			T76	18		T401	3		T387	102
values[15]	12764	1			T76	18		T401	1		T387	86
values[16]	12407	1			T76	18		T401	2		T387	112
values[17]	12083	1			T76	18		T387	127		T509	16
values[18]	11408	1			T76	18		T387	70		T509	16
values[19]	11078	1			T76	19		T387	65		T509	16
values[20]	10479	1			T76	18		T387	76		T509	16
values[21]	10145	1			T76	18		T387	95		T509	16
values[22]	9954	1			T76	18		T387	78		T509	17
values[23]	9354	1			T76	18		T387	59		T509	16
values[24]	8871	1			T76	18		T387	47		T509	17
values[25]	8731	1			T76	18		T387	39		T509	16
values[26]	8255	1			T76	18		T387	68		T509	16
values[27]	7598	1			T76	18		T387	54		T509	16
values[28]	7031	1			T76	18		T387	71		T509	16
values[29]	6633	1			T76	18		T387	49		T509	17
values[30]	6390	1			T76	18		T387	45		T509	16
values[31]	6051	1			T76	18		T387	29		T509	16
values[32]	5843	1			T76	18		T387	18		T509	16
values[33]	5137	1			T76	18		T387	10		T509	16
values[34]	4957	1			T76	19		T387	11		T509	16
values[35]	4666	1			T76	18		T387	17		T509	16
values[36]	4436	1			T76	18		T387	12		T509	16
values[37]	4090	1			T76	18		T387	11		T509	16
values[38]	4014	1			T76	18		T387	8		T509	16
values[39]	3838	1			T76	18		T387	4		T509	16
values[40]	3700	1			T76	18		T387	7		T509	16
values[41]	3607	1			T76	18		T387	6		T509	16
values[42]	3578	1			T76	18		T387	6		T509	17
values[43]	3477	1			T76	18		T387	6		T509	16
values[44]	3487	1			T76	18		T387	4		T509	16
values[45]	3434	1			T76	18		T387	7		T509	16
values[46]	3283	1			T76	18		T387	11		T509	16
values[47]	3310	1			T76	20		T387	10		T509	16
values[48]	3329	1			T76	20		T387	3		T509	16
values[49]	3286	1			T76	18		T387	1		T509	16
values[50]	3192	1			T76	19		T387	1		T509	16
values[51]	3082	1			T76	18		T387	2		T509	17
values[52]	3247	1			T76	18		T387	1		T509	16
values[53]	3163	1			T76	19		T509	16		T470	1
values[54]	2991	1			T76	18		T509	16		T470	4
values[55]	2863	1			T76	18		T509	16		T470	2
values[56]	2868	1			T76	18		T509	16		T470	3
values[57]	2759	1			T76	18		T509	16		T470	2
values[58]	2791	1			T76	18		T509	16		T470	4
values[59]	2830	1			T76	19		T509	16		T470	7
values[60]	2771	1			T76	19		T509	16		T470	10
values[61]	2940	1			T76	18		T509	16		T470	6
values[62]	4273	1			T76	19		T509	16		T470	8
values[63]	19445	1			T76	310		T509	16		T470	3
values[64]	211570	1			T76	3060		T509	3042		T470	15