Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2095874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35203765

1

T4

39093

T5

11815

T6

5747

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25601744	1			T4	25193		T5	5537		T6	801
values[0x0]	9890722	1			T4	13900		T5	6278		T6	4946
values[0x1]	1807173	1			T4	3249		T5	558		T6	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	453366	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36846273

1

T4

42342

T5

12373

T6

5810

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17711116	1			T4	21176		T5	6187		T6	2906
valid_sources[0x01]	17709608	1			T4	21166		T5	6186		T6	2904
valid_sources[0x02]	29365	1			T31	1		T117	378		T360	444
valid_sources[0x03]	30266	1			T31	1		T117	362		T360	366
valid_sources[0x04]	30469	1			T117	402		T360	309		T815	252
valid_sources[0x05]	35455	1			T31	2		T117	342		T360	381
valid_sources[0x06]	29237	1			T78	2		T186	4		T117	297
valid_sources[0x07]	30143	1			T31	1		T187	2		T117	317
valid_sources[0x08]	29572	1			T187	3		T117	285		T360	419
valid_sources[0x09]	31699	1			T117	471		T360	497		T815	307
valid_sources[0x0a]	29857	1			T187	1		T117	394		T360	409
valid_sources[0x0b]	30317	1			T186	8		T117	440		T360	453
valid_sources[0x0c]	29868	1			T31	1		T117	440		T360	461
valid_sources[0x0d]	29904	1			T31	1		T78	3		T117	504
valid_sources[0x0e]	29670	1			T117	343		T360	354		T815	272
valid_sources[0x0f]	29941	1			T31	3		T78	4		T187	1
valid_sources[0x10]	29979	1			T117	404		T360	500		T815	204
valid_sources[0x11]	30389	1			T33	39		T117	406		T360	453
valid_sources[0x12]	30286	1			T31	1		T78	1		T117	421
valid_sources[0x13]	29788	1			T117	426		T360	434		T815	253
valid_sources[0x14]	30375	1			T117	477		T360	378		T815	203
valid_sources[0x15]	30504	1			T31	2		T187	4		T117	383
valid_sources[0x16]	33264	1			T117	391		T360	361		T815	205
valid_sources[0x17]	30579	1			T78	1		T117	395		T360	396
valid_sources[0x18]	29891	1			T117	481		T360	389		T815	289
valid_sources[0x19]	30109	1			T117	426		T360	427		T815	207
valid_sources[0x1a]	28905	1			T31	1		T187	1		T117	404
valid_sources[0x1b]	29456	1			T31	1		T186	3		T117	384
valid_sources[0x1c]	30196	1			T31	2		T117	435		T360	347
valid_sources[0x1d]	30435	1			T187	3		T117	496		T360	411
valid_sources[0x1e]	29674	1			T31	2		T78	4		T187	1
valid_sources[0x1f]	29762	1			T31	1		T187	1		T117	354
valid_sources[0x20]	29368	1			T78	5		T117	303		T360	409

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25107644

1

T4

25193

T5

5537

T6

801

values[0x0]

all_enables

biggest_size

9855330

1

T4

13900

T5

6278

T6

4946

values[0x1]

all_enables

biggest_size

240791

1

T31

25

T33

17

T78

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2758274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

435995

1

T75

216

T76

634

T77

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1082025	1			T75	586		T76	1453		T77	66
values[0x0]	1031744	1			T75	571		T76	1492		T77	61
values[0x1]	1080500	1			T75	586		T76	1527		T77	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2137037	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1057232

1

T75

532

T76

1433

T77

51

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49959	1			T75	47		T76	76		T77	1
valid_sources[0x01]	49573	1			T75	61		T76	60		T79	18
valid_sources[0x02]	51027	1			T75	15		T76	65		T79	36
valid_sources[0x03]	49423	1			T75	48		T76	65		T77	4
valid_sources[0x04]	50023	1			T76	62		T77	2		T79	43
valid_sources[0x05]	49734	1			T75	87		T76	67		T77	5
valid_sources[0x06]	49778	1			T75	19		T76	72		T77	1
valid_sources[0x07]	49464	1			T75	30		T76	67		T77	4
valid_sources[0x08]	49913	1			T75	24		T76	69		T77	5
valid_sources[0x09]	50144	1			T75	21		T76	51		T77	2
valid_sources[0x0a]	49559	1			T75	41		T76	74		T77	3
valid_sources[0x0b]	51309	1			T75	32		T76	78		T77	6
valid_sources[0x0c]	49836	1			T75	16		T76	54		T77	5
valid_sources[0x0d]	50016	1			T75	28		T76	80		T77	2
valid_sources[0x0e]	49269	1			T75	49		T76	63		T77	1
valid_sources[0x0f]	49100	1			T76	67		T77	5		T79	26
valid_sources[0x10]	49641	1			T75	25		T76	65		T77	4
valid_sources[0x11]	48700	1			T75	24		T76	71		T77	1
valid_sources[0x12]	49144	1			T75	12		T76	73		T77	5
valid_sources[0x13]	49931	1			T75	27		T76	69		T77	2
valid_sources[0x14]	49526	1			T75	25		T76	68		T77	2
valid_sources[0x15]	51087	1			T75	48		T76	73		T77	3
valid_sources[0x16]	50841	1			T75	9		T76	83		T77	4
valid_sources[0x17]	50057	1			T75	44		T76	84		T77	5
valid_sources[0x18]	50347	1			T75	33		T76	89		T77	4
valid_sources[0x19]	49522	1			T75	53		T76	82		T77	5
valid_sources[0x1a]	49285	1			T75	15		T76	68		T77	3
valid_sources[0x1b]	50674	1			T75	69		T76	69		T77	6
valid_sources[0x1c]	50035	1			T76	79		T77	7		T79	50
valid_sources[0x1d]	50755	1			T75	9		T76	69		T77	5
valid_sources[0x1e]	49236	1			T75	10		T76	69		T77	2
valid_sources[0x1f]	50177	1			T75	9		T76	59		T77	4
valid_sources[0x20]	49706	1			T75	29		T76	78		T77	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45943

1

T75

19

T76

63

T77

2

values[0x0]

all_enables

biggest_size

344361

1

T75

166

T76

516

T77

17

values[0x1]

all_enables

biggest_size

45691

1

T75

31

T76

55

T77

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2939681	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

477663

1

T75

255

T76

605

T77

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1170597	1			T75	618		T76	1368		T77	42
values[0x0]	1078603	1			T75	574		T76	1347		T77	55
values[0x1]	1168144	1			T75	606		T76	1405		T77	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2256753	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1160591

1

T75

615

T76

1398

T77

57

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53689	1			T75	40		T76	62		T79	49
valid_sources[0x01]	52491	1			T75	60		T76	64		T79	43
valid_sources[0x02]	53523	1			T75	16		T76	68		T77	6
valid_sources[0x03]	52870	1			T75	38		T76	47		T79	40
valid_sources[0x04]	54465	1			T76	61		T77	2		T79	45
valid_sources[0x05]	53615	1			T75	90		T76	69		T77	9
valid_sources[0x06]	53640	1			T75	30		T76	68		T77	3
valid_sources[0x07]	54124	1			T75	46		T76	76		T77	2
valid_sources[0x08]	53620	1			T75	38		T76	68		T79	33
valid_sources[0x09]	54061	1			T75	22		T76	60		T77	1
valid_sources[0x0a]	52906	1			T75	30		T76	57		T77	5
valid_sources[0x0b]	52853	1			T75	16		T76	57		T77	8
valid_sources[0x0c]	52050	1			T75	32		T76	52		T77	6
valid_sources[0x0d]	53110	1			T75	13		T76	63		T79	53
valid_sources[0x0e]	53762	1			T75	55		T76	61		T79	37
valid_sources[0x0f]	53596	1			T76	55		T77	5		T79	39
valid_sources[0x10]	53928	1			T75	44		T76	72		T77	2
valid_sources[0x11]	53538	1			T75	35		T76	45		T77	8
valid_sources[0x12]	53399	1			T75	16		T76	48		T79	35
valid_sources[0x13]	53855	1			T75	36		T76	72		T77	7
valid_sources[0x14]	53373	1			T75	25		T76	54		T77	1
valid_sources[0x15]	54398	1			T75	56		T76	93		T79	52
valid_sources[0x16]	53764	1			T75	19		T76	66		T77	10
valid_sources[0x17]	53034	1			T75	21		T76	75		T79	40
valid_sources[0x18]	54459	1			T75	12		T76	63		T77	1
valid_sources[0x19]	52699	1			T75	42		T76	81		T79	42
valid_sources[0x1a]	52745	1			T75	37		T76	56		T77	8
valid_sources[0x1b]	54164	1			T75	70		T76	74		T79	49
valid_sources[0x1c]	53131	1			T76	79		T79	44		T492	4
valid_sources[0x1d]	54822	1			T75	8		T76	66		T77	4
valid_sources[0x1e]	53515	1			T75	5		T76	67		T79	56
valid_sources[0x1f]	53458	1			T75	15		T76	55		T77	1
valid_sources[0x20]	53415	1			T75	10		T76	63		T79	50

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50264

1

T75

32

T76

62

T79

36

values[0x0]

all_enables

biggest_size

377496

1

T75

201

T76

478

T77

22

values[0x1]

all_enables

biggest_size

49903

1

T75

22

T76

65

T77

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2783194	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

439837

1

T75

267

T76

582

T77

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1090455	1			T75	592		T76	1533		T77	56
values[0x0]	1040868	1			T75	607		T76	1480		T77	58
values[0x1]	1091708	1			T75	599		T76	1486		T77	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2155159	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1067872

1

T75

621

T76

1423

T77

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50043	1			T75	40		T76	64		T77	8
valid_sources[0x01]	49788	1			T75	73		T76	69		T77	1
valid_sources[0x02]	50425	1			T75	20		T76	63		T79	28
valid_sources[0x03]	50097	1			T75	50		T76	56		T79	40
valid_sources[0x04]	49518	1			T76	66		T77	3		T79	36
valid_sources[0x05]	50278	1			T75	87		T76	65		T79	52
valid_sources[0x06]	50605	1			T75	15		T76	69		T77	3
valid_sources[0x07]	50415	1			T75	27		T76	74		T77	2
valid_sources[0x08]	50858	1			T75	43		T76	67		T79	14
valid_sources[0x09]	51097	1			T75	17		T76	70		T77	1
valid_sources[0x0a]	49994	1			T75	39		T76	72		T79	41
valid_sources[0x0b]	50556	1			T75	20		T76	59		T79	52
valid_sources[0x0c]	50625	1			T75	35		T76	67		T79	53
valid_sources[0x0d]	50986	1			T75	14		T76	87		T79	31
valid_sources[0x0e]	49418	1			T75	53		T76	76		T77	4
valid_sources[0x0f]	50123	1			T76	66		T79	30		T116	1
valid_sources[0x10]	50065	1			T75	28		T76	81		T77	4
valid_sources[0x11]	49975	1			T75	23		T76	60		T79	40
valid_sources[0x12]	50494	1			T75	7		T76	74		T77	1
valid_sources[0x13]	50022	1			T75	25		T76	74		T77	1
valid_sources[0x14]	50099	1			T75	21		T76	74		T79	52
valid_sources[0x15]	50882	1			T75	60		T76	79		T77	2
valid_sources[0x16]	50443	1			T75	10		T76	60		T79	30
valid_sources[0x17]	50580	1			T75	36		T76	72		T77	11
valid_sources[0x18]	51318	1			T75	27		T76	63		T79	50
valid_sources[0x19]	49290	1			T75	66		T76	77		T79	34
valid_sources[0x1a]	51243	1			T75	13		T76	85		T77	14
valid_sources[0x1b]	51638	1			T75	74		T76	73		T77	2
valid_sources[0x1c]	51032	1			T76	73		T79	49		T116	1
valid_sources[0x1d]	51566	1			T75	17		T76	75		T77	4
valid_sources[0x1e]	50058	1			T75	8		T76	69		T77	1
valid_sources[0x1f]	49511	1			T75	19		T76	71		T77	8
valid_sources[0x20]	51416	1			T75	27		T76	68		T77	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46118

1

T75

26

T76

53

T77

2

values[0x0]

all_enables

biggest_size

347407

1

T75

220

T76

472

T77

14

values[0x1]

all_enables

biggest_size

46312

1

T75

21

T76

57

T77

2