Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503075826	59982832	0	0
DepthKnown_A	503075826	502970219	0	0
RvalidKnown_A	503075826	502970219	0	0
WreadyKnown_A	503075826	502970219	0	0
gen_passthru_fifo.paramCheckPass	1007	1007	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	59982832	0	0
T4	946072	504566	0	0
T5	147942	16576	0	0
T6	162251	11207	0	0
T16	609657	58166	0	0
T17	189851	37145	0	0
T41	237865	30208	0	0
T52	122736	137547	0	0
T56	216739	28029	0	0
T62	88876	9679	0	0
T83	227574	185342	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503075826	45165271	0	0
DepthKnown_A	503075826	502970219	0	0
RvalidKnown_A	503075826	502970219	0	0
WreadyKnown_A	503075826	502970219	0	0
gen_passthru_fifo.paramCheckPass	1007	1007	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	45165271	0	0
T4	946072	256174	0	0
T5	147942	12636	0	0
T6	162251	7492	0	0
T16	609657	54358	0	0
T17	189851	27051	0	0
T41	237865	21202	0	0
T52	122736	119044	0	0
T56	216739	25397	0	0
T62	88876	7412	0	0
T83	227574	91863	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503075826	42455778	0	0
DepthKnown_A	503075826	502970219	0	0
RvalidKnown_A	503075826	502970219	0	0
WreadyKnown_A	503075826	502970219	0	0
gen_passthru_fifo.paramCheckPass	1007	1007	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	42455778	0	0
T4	946072	45493	0	0
T5	147942	12669	0	0
T6	162251	6064	0	0
T16	609657	65479	0	0
T17	189851	21699	0	0
T41	237865	15436	0	0
T52	122736	172371	0	0
T56	216739	7398	0	0
T62	88876	8261	0	0
T83	227574	7734	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	503075826	35448968	0	0
DepthKnown_A	503075826	502970219	0	0
RvalidKnown_A	503075826	502970219	0	0
WreadyKnown_A	503075826	502970219	0	0
gen_passthru_fifo.paramCheckPass	1007	1007	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	35448968	0	0
T4	946072	42342	0	0
T5	147942	12373	0	0
T6	162251	5810	0	0
T16	609657	65280	0	0
T17	189851	21142	0	0
T41	237865	15043	0	0
T52	122736	110966	0	0
T56	216739	7196	0	0
T62	88876	7902	0	0
T83	227574	6326	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569629966	88823	0	0
DepthKnown_A	569629966	569512637	0	0
RvalidKnown_A	569629966	569512637	0	0
WreadyKnown_A	569629966	569512637	0	0
gen_passthru_fifo.paramCheckPass	2896	2896	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	88823	0	0
T4	946072	98	0	0
T5	147942	94	0	0
T6	162251	34	0	0
T16	609657	53	0	0
T17	189851	15	0	0
T41	237865	151	0	0
T52	122736	34	0	0
T56	216739	78	0	0
T62	88876	14	0	0
T83	227574	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2896	2896	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569629966	92910	0	0
DepthKnown_A	569629966	569512637	0	0
RvalidKnown_A	569629966	569512637	0	0
WreadyKnown_A	569629966	569512637	0	0
gen_passthru_fifo.paramCheckPass	2896	2896	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	92910	0	0
T4	946072	98	0	0
T5	147942	94	0	0
T6	162251	34	0	0
T16	609657	53	0	0
T17	189851	15	0	0
T41	237865	151	0	0
T52	122736	34	0	0
T56	216739	78	0	0
T62	88876	14	0	0
T83	227574	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2896	2896	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569629966	51356	0	0
DepthKnown_A	569629966	569512637	0	0
RvalidKnown_A	569629966	569512637	0	0
WreadyKnown_A	569629966	569512637	0	0
gen_passthru_fifo.paramCheckPass	2896	2896	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	51356	0	0
T4	946072	98	0	0
T5	147942	93	0	0
T6	162251	32	0	0
T16	609657	52	0	0
T17	189851	12	0	0
T41	237865	95	0	0
T52	122736	5	0	0
T56	216739	77	0	0
T62	88876	13	0	0
T83	227574	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2896	2896	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569629966	51356	0	0
DepthKnown_A	569629966	569512637	0	0
RvalidKnown_A	569629966	569512637	0	0
WreadyKnown_A	569629966	569512637	0	0
gen_passthru_fifo.paramCheckPass	2896	2896	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	51356	0	0
T4	946072	98	0	0
T5	147942	93	0	0
T6	162251	32	0	0
T16	609657	52	0	0
T17	189851	12	0	0
T41	237865	95	0	0
T52	122736	5	0	0
T56	216739	77	0	0
T62	88876	13	0	0
T83	227574	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2896	2896	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569629966	37467	0	0
DepthKnown_A	569629966	569512637	0	0
RvalidKnown_A	569629966	569512637	0	0
WreadyKnown_A	569629966	569512637	0	0
gen_passthru_fifo.paramCheckPass	2896	2896	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	37467	0	0
T5	147942	1	0	0
T6	162251	2	0	0
T16	609657	1	0	0
T17	189851	3	0	0
T41	237865	56	0	0
T52	122736	29	0	0
T56	216739	1	0	0
T58	120725	5	0	0
T62	88876	1	0	0
T83	227574	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2896	2896	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	569629966	41554	0	0
DepthKnown_A	569629966	569512637	0	0
RvalidKnown_A	569629966	569512637	0	0
WreadyKnown_A	569629966	569512637	0	0
gen_passthru_fifo.paramCheckPass	2896	2896	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	41554	0	0
T5	147942	1	0	0
T6	162251	2	0	0
T16	609657	1	0	0
T17	189851	3	0	0
T41	237865	56	0	0
T52	122736	29	0	0
T56	216739	1	0	0
T58	120725	5	0	0
T62	88876	1	0	0
T83	227574	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	569629966	569512637	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2896	2896	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0