Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.98 100.00 99.90 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.98 100.00 99.90 100.00 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15601560100.00
ALWAYS6844100.00
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CONT_ASSIGN1659311100.00
CONT_ASSIGN1662711100.00
CONT_ASSIGN1664111100.00
ALWAYS16647203203100.00
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CONT_ASSIGN1940200
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WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16579 1 1
16593 1 1
16627 1 1
16641 1 1
16647 1 1
16648 1 1
16649 1 1
16650 1 1
16651 1 1
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19314 1 1
19315 1 1
19316 1 1
19317 1 1
19318 1 1
19319 1 1
19320 1 1
19321 1 1
19322 1 1
19323 1 1
19324 1 1
19325 1 1
19326 1 1
19327 1 1
19328 1 1
19329 1 1
19330 1 1
19331 1 1
19332 1 1
19333 1 1
19334 1 1
19335 1 1
19336 1 1
19337 1 1
19338 1 1
19339 1 1
19340 1 1
19341 1 1
19342 1 1
19343 1 1
19347 1 1
19348 1 1
19349 1 1
19350 1 1
19351 1 1
19352 1 1
19353 1 1
19354 1 1
19355 1 1
19356 1 1
19357 1 1
19358 1 1
19359 1 1
19360 1 1
19361 1 1
19362 1 1
19363 1 1
19364 1 1
19365 1 1
19366 1 1
19367 1 1
19368 1 1
19369 1 1
19370 1 1
19371 1 1
19372 1 1
19376 1 1
19380 1 1
19384 1 1
19388 1 1
19402 unreachable
19410 1 1
19411 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions2023202199.90
Logical2023202199.90
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1683699.74
16837-16856100.00
16856100.00
16856-17359100.00
17362-1800899.74

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 208 208 100.00
TERNARY 16852 2 2 100.00
IF 68 3 3 100.00
CASE 18222 203 203 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16852 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T5,T16,T17
0 Covered T4,T5,T6


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T406,T411,T412
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 18222 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T5,T16,T17
addr_hit[1] Covered T202,T203,T204
addr_hit[2] Covered T202,T203,T204
addr_hit[3] Covered T202,T203,T204
addr_hit[4] Covered T202,T203,T204
addr_hit[5] Covered T202,T203,T204
addr_hit[6] Covered T202,T203,T204
addr_hit[7] Covered T202,T203,T204
addr_hit[8] Covered T202,T203,T204
addr_hit[9] Covered T202,T203,T204
addr_hit[10] Covered T305,T31,T199
addr_hit[11] Covered T305,T31,T199
addr_hit[12] Covered T305,T31,T199
addr_hit[13] Covered T305,T31,T199
addr_hit[14] Covered T305,T31,T199
addr_hit[15] Covered T305,T31,T199
addr_hit[16] Covered T305,T31,T199
addr_hit[17] Covered T305,T31,T199
addr_hit[18] Covered T305,T31,T199
addr_hit[19] Covered T140,T141,T316
addr_hit[20] Covered T140,T141,T316
addr_hit[21] Covered T140,T141,T316
addr_hit[22] Covered T140,T141,T316
addr_hit[23] Covered T140,T141,T316
addr_hit[24] Covered T140,T141,T316
addr_hit[25] Covered T140,T141,T316
addr_hit[26] Covered T140,T141,T316
addr_hit[27] Covered T140,T141,T316
addr_hit[28] Covered T16,T25,T26
addr_hit[29] Covered T16,T25,T26
addr_hit[30] Covered T16,T25,T26
addr_hit[31] Covered T16,T25,T26
addr_hit[32] Covered T16,T25,T26
addr_hit[33] Covered T16,T25,T26
addr_hit[34] Covered T16,T25,T26
addr_hit[35] Covered T16,T25,T26
addr_hit[36] Covered T16,T25,T26
addr_hit[37] Covered T305,T31,T149
addr_hit[38] Covered T305,T31,T149
addr_hit[39] Covered T305,T31,T149
addr_hit[40] Covered T305,T31,T149
addr_hit[41] Covered T305,T31,T149
addr_hit[42] Covered T305,T31,T149
addr_hit[43] Covered T305,T31,T149
addr_hit[44] Covered T305,T31,T149
addr_hit[45] Covered T305,T31,T149
addr_hit[46] Covered T305,T31,T149
addr_hit[47] Covered T305,T31,T149
addr_hit[48] Covered T305,T31,T149
addr_hit[49] Covered T305,T31,T149
addr_hit[50] Covered T305,T31,T149
addr_hit[51] Covered T305,T31,T149
addr_hit[52] Covered T305,T31,T149
addr_hit[53] Covered T305,T31,T149
addr_hit[54] Covered T305,T31,T149
addr_hit[55] Covered T305,T31,T149
addr_hit[56] Covered T305,T31,T149
addr_hit[57] Covered T305,T31,T149
addr_hit[58] Covered T305,T31,T149
addr_hit[59] Covered T305,T31,T149
addr_hit[60] Covered T305,T31,T149
addr_hit[61] Covered T305,T31,T149
addr_hit[62] Covered T305,T31,T149
addr_hit[63] Covered T305,T31,T149
addr_hit[64] Covered T305,T31,T149
addr_hit[65] Covered T305,T31,T149
addr_hit[66] Covered T305,T31,T149
addr_hit[67] Covered T305,T31,T149
addr_hit[68] Covered T305,T31,T149
addr_hit[69] Covered T5,T22,T305
addr_hit[70] Covered T5,T305,T31
addr_hit[71] Covered T5,T305,T31
addr_hit[72] Covered T5,T22,T305
addr_hit[73] Covered T5,T22,T305
addr_hit[74] Covered T5,T305,T31
addr_hit[75] Covered T305,T31,T149
addr_hit[76] Covered T305,T31,T149
addr_hit[77] Covered T305,T31,T149
addr_hit[78] Covered T305,T31,T149
addr_hit[79] Covered T305,T31,T149
addr_hit[80] Covered T305,T31,T149
addr_hit[81] Covered T305,T31,T149
addr_hit[82] Covered T305,T31,T149
addr_hit[83] Covered T305,T31,T149
addr_hit[84] Covered T305,T31,T149
addr_hit[85] Covered T305,T31,T149
addr_hit[86] Covered T305,T31,T149
addr_hit[87] Covered T305,T31,T149
addr_hit[88] Covered T305,T31,T149
addr_hit[89] Covered T305,T31,T149
addr_hit[90] Covered T305,T31,T149
addr_hit[91] Covered T305,T31,T149
addr_hit[92] Covered T305,T31,T149
addr_hit[93] Covered T305,T31,T149
addr_hit[94] Covered T305,T31,T149
addr_hit[95] Covered T305,T31,T149
addr_hit[96] Covered T305,T31,T149
addr_hit[97] Covered T305,T31,T149
addr_hit[98] Covered T305,T31,T149
addr_hit[99] Covered T305,T31,T149
addr_hit[100] Covered T305,T31,T149
addr_hit[101] Covered T305,T31,T149
addr_hit[102] Covered T305,T31,T149
addr_hit[103] Covered T305,T31,T149
addr_hit[104] Covered T305,T31,T149
addr_hit[105] Covered T305,T31,T149
addr_hit[106] Covered T305,T31,T149
addr_hit[107] Covered T305,T31,T149
addr_hit[108] Covered T305,T31,T149
addr_hit[109] Covered T305,T31,T149
addr_hit[110] Covered T305,T31,T149
addr_hit[111] Covered T305,T31,T149
addr_hit[112] Covered T305,T31,T149
addr_hit[113] Covered T305,T31,T149
addr_hit[114] Covered T305,T31,T149
addr_hit[115] Covered T305,T31,T149
addr_hit[116] Covered T305,T31,T149
addr_hit[117] Covered T305,T31,T149
addr_hit[118] Covered T305,T31,T149
addr_hit[119] Covered T305,T31,T149
addr_hit[120] Covered T305,T31,T149
addr_hit[121] Covered T305,T31,T149
addr_hit[122] Covered T200,T337,T305
addr_hit[123] Covered T200,T337,T305
addr_hit[124] Covered T305,T31,T149
addr_hit[125] Covered T305,T31,T149
addr_hit[126] Covered T305,T31,T149
addr_hit[127] Covered T41,T63,T64
addr_hit[128] Covered T41,T63,T64
addr_hit[129] Covered T41,T63,T64
addr_hit[130] Covered T41,T63,T64
addr_hit[131] Covered T22,T305,T31
addr_hit[132] Covered T22,T305,T31
addr_hit[133] Covered T305,T31,T149
addr_hit[134] Covered T305,T31,T149
addr_hit[135] Covered T305,T31,T149
addr_hit[136] Covered T305,T31,T149
addr_hit[137] Covered T305,T31,T149
addr_hit[138] Covered T305,T31,T149
addr_hit[139] Covered T305,T31,T149
addr_hit[140] Covered T305,T31,T149
addr_hit[141] Covered T305,T31,T149
addr_hit[142] Covered T305,T31,T149
addr_hit[143] Covered T305,T31,T149
addr_hit[144] Covered T305,T31,T149
addr_hit[145] Covered T305,T31,T149
addr_hit[146] Covered T305,T31,T149
addr_hit[147] Covered T305,T31,T149
addr_hit[148] Covered T305,T31,T149
addr_hit[149] Covered T305,T31,T149
addr_hit[150] Covered T305,T31,T149
addr_hit[151] Covered T305,T31,T149
addr_hit[152] Covered T305,T31,T149
addr_hit[153] Covered T1,T97,T98
addr_hit[154] Covered T305,T31,T191
addr_hit[155] Covered T103,T305,T31
addr_hit[156] Covered T41,T63,T64
addr_hit[157] Covered T41,T63,T64
addr_hit[158] Covered T134,T135,T343
addr_hit[159] Covered T305,T31,T149
addr_hit[160] Covered T17,T305,T31
addr_hit[161] Covered T17,T305,T31
addr_hit[162] Covered T17,T305,T31
addr_hit[163] Covered T17,T305,T31
addr_hit[164] Covered T17,T305,T31
addr_hit[165] Covered T305,T31,T149
addr_hit[166] Covered T296,T309,T344
addr_hit[167] Covered T296,T309,T344
addr_hit[168] Covered T305,T31,T149
addr_hit[169] Covered T305,T31,T149
addr_hit[170] Covered T305,T31,T149
addr_hit[171] Covered T305,T31,T149
addr_hit[172] Covered T305,T31,T322
addr_hit[173] Covered T305,T31,T149
addr_hit[174] Covered T305,T31,T149
addr_hit[175] Covered T113,T305,T31
addr_hit[176] Covered T305,T31,T149
addr_hit[177] Covered T305,T31,T149
addr_hit[178] Covered T305,T31,T149
addr_hit[179] Covered T305,T31,T149
addr_hit[180] Covered T305,T31,T149
addr_hit[181] Covered T305,T31,T149
addr_hit[182] Covered T113,T305,T31
addr_hit[183] Covered T305,T31,T149
addr_hit[184] Covered T113,T305,T31
addr_hit[185] Covered T305,T31,T149
addr_hit[186] Covered T31,T360,T365
addr_hit[187] Covered T31,T117,T360
addr_hit[188] Covered T31,T117,T360
addr_hit[189] Covered T31,T117,T360
addr_hit[190] Covered T298,T31,T649
addr_hit[191] Covered T31,T360,T365
addr_hit[192] Covered T16,T202,T25
addr_hit[193] Covered T16,T25,T26
addr_hit[194] Covered T5,T22,T305
addr_hit[195] Covered T41,T63,T64
addr_hit[196] Covered T41,T134,T1
addr_hit[197] Covered T17,T296,T309
addr_hit[198] Covered T16,T17,T41
addr_hit[199] Covered T5,T16,T17
addr_hit[200] Covered T31,T236,T237
addr_hit[201] Covered T58,T59,T31
default Covered T75,T77,T79


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 569629966 197625 0 0
reAfterRv 569629966 197625 0 0
rePulse 569629966 124025 0 0
wePulse 569629966 73600 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 569629966 197625 0 0
T1 0 40 0 0
T2 0 6 0 0
T5 147942 98 0 0
T6 162251 0 0 0
T16 609657 48 0 0
T17 189851 110 0 0
T41 237865 44 0 0
T52 122736 0 0 0
T56 216739 0 0 0
T58 120725 1 0 0
T62 88876 0 0 0
T83 227574 0 0 0
T97 0 8 0 0
T98 0 8 0 0
T134 0 24 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 569629966 197625 0 0
T1 0 40 0 0
T2 0 6 0 0
T5 147942 98 0 0
T6 162251 0 0 0
T16 609657 48 0 0
T17 189851 110 0 0
T41 237865 44 0 0
T52 122736 0 0 0
T56 216739 0 0 0
T58 120725 1 0 0
T62 88876 0 0 0
T83 227574 0 0 0
T97 0 8 0 0
T98 0 8 0 0
T134 0 24 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 569629966 124025 0 0
T1 0 13 0 0
T2 0 2 0 0
T5 147942 46 0 0
T6 162251 0 0 0
T16 609657 19 0 0
T17 189851 52 0 0
T41 237865 14 0 0
T52 122736 0 0 0
T56 216739 0 0 0
T58 120725 0 0 0
T62 88876 0 0 0
T63 0 14 0 0
T83 227574 0 0 0
T97 0 3 0 0
T98 0 3 0 0
T134 0 11 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 569629966 73600 0 0
T1 0 27 0 0
T2 0 4 0 0
T5 147942 52 0 0
T6 162251 0 0 0
T16 609657 29 0 0
T17 189851 58 0 0
T41 237865 30 0 0
T52 122736 0 0 0
T56 216739 0 0 0
T58 120725 1 0 0
T62 88876 0 0 0
T83 227574 0 0 0
T97 0 5 0 0
T98 0 5 0 0
T134 0 13 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%