Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_lc_or_hardened

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_lc_or_hardened

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	3	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	9063	9063	0	0
OutputsKnown_A	1884335098	1879451510	0	0
gen_flops.OutputDelay_A	1507970764	1505047000	0	17904
gen_no_flops.OutputDelay_A	376364334	374361888	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9063	9063	0	0
T4	9	9	0	0
T5	9	9	0	0
T6	9	9	0	0
T16	9	9	0	0
T17	9	9	0	0
T41	9	9	0	0
T52	9	9	0	0
T56	9	9	0	0
T62	9	9	0	0
T83	9	9	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1884335098	1879451510	0	0
T4	3531691	3508569	0	0
T5	550698	546921	0	0
T6	620091	613448	0	0
T16	2249322	2246041	0	0
T17	705062	701124	0	0
T41	884201	880285	0	0
T52	2312922	2310154	0	0
T56	812122	807266	0	0
T62	333978	329550	0	0
T83	842528	839948	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1507970764	1505047000	0	17904
T4	2829028	2815014	0	18
T5	441492	439266	0	18
T6	493410	489392	0	18
T16	1807890	1805938	0	18
T17	565622	563298	0	18
T41	709142	706756	0	18
T52	1426872	1425268	0	18
T56	649846	647000	0	18
T62	267024	264426	0	18
T83	676508	674960	0	18

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376364334	374361888	0	0
T4	702663	693291	0	0
T5	109206	107631	0	0
T6	126681	123984	0	0
T16	441432	440079	0	0
T17	139440	137802	0	0
T41	175059	173481	0	0
T52	886050	884868	0	0
T56	162276	160242	0	0
T62	66954	65100	0	0
T83	166020	164964	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	125454778	124787296	0	0
gen_flops.OutputDelay_A	125454778	124780392	0	2985

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124787296	0	0
T4	234221	231097	0	0
T5	36402	35877	0	0
T6	42227	41328	0	0
T16	147144	146693	0	0
T17	46480	45934	0	0
T41	58353	57827	0	0
T52	295350	294956	0	0
T56	54092	53414	0	0
T62	22318	21700	0	0
T83	55340	54988	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124780392	0	2985
T4	234221	231053	0	3
T5	36402	35873	0	3
T6	42227	41316	0	3
T16	147144	146689	0	3
T17	46480	45930	0	3
T41	58353	57819	0	3
T52	295350	294952	0	3
T56	54092	53410	0	3
T62	22318	21696	0	3
T83	55340	54984	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	125454778	124787296	0	0
gen_flops.OutputDelay_A	125454778	124780392	0	2985

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124787296	0	0
T4	234221	231097	0	0
T5	36402	35877	0	0
T6	42227	41328	0	0
T16	147144	146693	0	0
T17	46480	45934	0	0
T41	58353	57827	0	0
T52	295350	294956	0	0
T56	54092	53414	0	0
T62	22318	21700	0	0
T83	55340	54988	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124780392	0	2985
T4	234221	231053	0	3
T5	36402	35873	0	3
T6	42227	41316	0	3
T16	147144	146689	0	3
T17	46480	45930	0	3
T41	58353	57819	0	3
T52	295350	294952	0	3
T56	54092	53410	0	3
T62	22318	21696	0	3
T83	55340	54984	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	125454778	124787296	0	0
gen_flops.OutputDelay_A	125454778	124780392	0	2985

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124787296	0	0
T4	234221	231097	0	0
T5	36402	35877	0	0
T6	42227	41328	0	0
T16	147144	146693	0	0
T17	46480	45934	0	0
T41	58353	57827	0	0
T52	295350	294956	0	0
T56	54092	53414	0	0
T62	22318	21700	0	0
T83	55340	54988	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124780392	0	2985
T4	234221	231053	0	3
T5	36402	35873	0	3
T6	42227	41316	0	3
T16	147144	146689	0	3
T17	46480	45930	0	3
T41	58353	57819	0	3
T52	295350	294952	0	3
T56	54092	53410	0	3
T62	22318	21696	0	3
T83	55340	54984	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	125454778	124787296	0	0
gen_flops.OutputDelay_A	125454778	124780392	0	2985

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124787296	0	0
T4	234221	231097	0	0
T5	36402	35877	0	0
T6	42227	41328	0	0
T16	147144	146693	0	0
T17	46480	45934	0	0
T41	58353	57827	0	0
T52	295350	294956	0	0
T56	54092	53414	0	0
T62	22318	21700	0	0
T83	55340	54988	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124780392	0	2985
T4	234221	231053	0	3
T5	36402	35873	0	3
T6	42227	41316	0	3
T16	147144	146689	0	3
T17	46480	45930	0	3
T41	58353	57819	0	3
T52	295350	294952	0	3
T56	54092	53410	0	3
T62	22318	21696	0	3
T83	55340	54984	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	125454778	124787296	0	0
gen_no_flops.OutputDelay_A	125454778	124787296	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124787296	0	0
T4	234221	231097	0	0
T5	36402	35877	0	0
T6	42227	41328	0	0
T16	147144	146693	0	0
T17	46480	45934	0	0
T41	58353	57827	0	0
T52	295350	294956	0	0
T56	54092	53414	0	0
T62	22318	21700	0	0
T83	55340	54988	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124787296	0	0
T4	234221	231097	0	0
T5	36402	35877	0	0
T6	42227	41328	0	0
T16	147144	146693	0	0
T17	46480	45934	0	0
T41	58353	57827	0	0
T52	295350	294956	0	0
T56	54092	53414	0	0
T62	22318	21700	0	0
T83	55340	54988	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	125454778	124787296	0	0
gen_no_flops.OutputDelay_A	125454778	124787296	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124787296	0	0
T4	234221	231097	0	0
T5	36402	35877	0	0
T6	42227	41328	0	0
T16	147144	146693	0	0
T17	46480	45934	0	0
T41	58353	57827	0	0
T52	295350	294956	0	0
T56	54092	53414	0	0
T62	22318	21700	0	0
T83	55340	54988	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124787296	0	0
T4	234221	231097	0	0
T5	36402	35877	0	0
T6	42227	41328	0	0
T16	147144	146693	0	0
T17	46480	45934	0	0
T41	58353	57827	0	0
T52	295350	294956	0	0
T56	54092	53414	0	0
T62	22318	21700	0	0
T83	55340	54988	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	3	3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	125454778	124787296	0	0
gen_no_flops.OutputDelay_A	125454778	124787296	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124787296	0	0
T4	234221	231097	0	0
T5	36402	35877	0	0
T6	42227	41328	0	0
T16	147144	146693	0	0
T17	46480	45934	0	0
T41	58353	57827	0	0
T52	295350	294956	0	0
T56	54092	53414	0	0
T62	22318	21700	0	0
T83	55340	54988	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125454778	124787296	0	0
T4	234221	231097	0	0
T5	36402	35877	0	0
T6	42227	41328	0	0
T16	147144	146693	0	0
T17	46480	45934	0	0
T41	58353	57827	0	0
T52	295350	294956	0	0
T56	54092	53414	0	0
T62	22318	21700	0	0
T83	55340	54988	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	503075826	502970219	0	0
gen_flops.OutputDelay_A	503075826	502962716	0	2982

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502962716	0	2982
T4	946072	945401	0	3
T5	147942	147887	0	3
T6	162251	162064	0	3
T16	609657	609591	0	3
T17	189851	189789	0	3
T41	237865	237740	0	3
T52	122736	122730	0	3
T56	216739	216680	0	3
T62	88876	88821	0	3
T83	227574	227512	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	503075826	502970219	0	0
gen_flops.OutputDelay_A	503075826	502962716	0	2982

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T41	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502970219	0	0
T4	946072	945445	0	0
T5	147942	147891	0	0
T6	162251	162076	0	0
T16	609657	609595	0	0
T17	189851	189793	0	0
T41	237865	237748	0	0
T52	122736	122731	0	0
T56	216739	216684	0	0
T62	88876	88825	0	0
T83	227574	227516	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503075826	502962716	0	2982
T4	946072	945401	0	3
T5	147942	147887	0	3
T6	162251	162064	0	3
T16	609657	609591	0	3
T17	189851	189789	0	3
T41	237865	237740	0	3
T52	122736	122730	0	3
T56	216739	216680	0	3
T62	88876	88821	0	3
T83	227574	227512	0	3