Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.37	90.68		89.43			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T76,T77,T79	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T18,T207,T208	Yes	T18,T207,T208	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T207,T208	Yes	T18,T207,T208	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T75,T77,T116	Yes	T75,T77,T116	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T18,T64,T207	Yes	T18,T64,T207	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T6,T41,T27	Yes	T5,T6,T62	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T6,T41,T27	Yes	T5,T6,T62	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T6,T41,T27	Yes	T5,T6,T62	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T6,T41,T27	Yes	T5,T6,T62	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T69,T31,T66	Yes	T69,T31,T66	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T76,T77,T117	Yes	T75,T76,T77	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T76,T77	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T75,T79,T116	Yes	T75,T77,T79	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T77,T117	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T242	Yes	T69,T70,T242	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T5,T6,T62	Yes	T6,T41,T27	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T69,T70,T242	Yes	T69,T70,T242	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T5,T6,T62	Yes	T6,T41,T27	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T242	Yes	T69,T70,T242	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T62	Yes	T6,T41,T27	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T69,T70,T31	Yes	T69,T70,T31	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T4,T52,T53	Yes	T4,T52,T53	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T58,T59,T232	Yes	T58,T59,T232	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T59,T260	Yes	T58,T59,T260	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T58,T59,T260	Yes	T58,T59,T260	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T58,T59,T232	Yes	T58,T59,T232	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T58,T59,T260	Yes	T58,T59,T260	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T58,T59,T260	Yes	T58,T59,T260	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T58,T59,T260	Yes	T58,T59,T260	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T260,T261,T410	Yes	T260,T261,T410	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T75,T76,T77	Yes	T58,T59,T232	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T260,T261,T410	Yes	T58,T59,T260	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T75,T77,*T79	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T260,*T261,*T410	Yes	T260,T261,T410	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T58,T59,T260	Yes	T58,T59,T260	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T41,T63,T234	Yes	T41,T63,T234	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T31,*T75,*T76	Yes	T31,T75,T76	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T24,T183,T185	Yes	T24,T183,T185	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T197,T22,T31	Yes	T197,T22,T31	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T197,T22,T231	Yes	T58,T197,T59	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T197,T22,T31	Yes	T197,T22,T31	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T31,*T75,*T76	Yes	T31,T75,T76	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T197,*T22,*T31	Yes	T197,T22,T31	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T31,*T75,*T77	Yes	T31,T75,T77	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T197,T31,T368	Yes	T197,T31,T368	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T197,T31,T368	Yes	T58,T197,T59	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T197,T31,T368	Yes	T197,T31,T368	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T31,*T75,*T79	Yes	T31,T75,T77	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T197,*T31,*T368	Yes	T197,T31,T368	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T58,T27,T1	Yes	T58,T27,T1	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T58,T27,T1	Yes	T58,T27,T1	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T27,T1	Yes	T58,T27,T1	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T58,T27,T1	Yes	T58,T27,T1	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T58,T27,T1	Yes	T58,T27,T1	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T58,T27,T1	Yes	T58,T27,T1	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T33,*T75,*T79	Yes	T33,T75,T79	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T58,T27,T1	Yes	T58,T27,T1	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T58,T27,T1	Yes	T58,T27,T1	INPUT
tl_usbdev_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T197,T28,T61	Yes	T197,T28,T61	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T197,T28,T61	Yes	T197,T28,T61	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T58,T27,T1	Yes	T27,T1,T197	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T33,*T75,*T77	Yes	T33,T75,T77	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T58,*T27,*T1	Yes	T27,T1,T197	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T58,T27,T1	Yes	T58,T27,T1	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T6,T41	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T6,T17	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T76,T77,T117	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T75,*T77,*T117	Yes	T75,T77,T117	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T6,T41	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T296,T301,T255	Yes	T296,T301,T255	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	INPUT
tl_hmac_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T52,T53,T18	Yes	T52,T53,T18	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T53,T18	Yes	T52,T53,T18	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T52,T58,T53	Yes	T52,T53,T18	INPUT
tl_hmac_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T52,*T58,*T53	Yes	T52,T53,T18	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T6,T62	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T62,T58,T99	Yes	T62,T58,T99	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T83,T58	Yes	T62,T83,T58	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T62,T83,T58	Yes	T62,T83,T58	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T62,T58,T99	Yes	T62,T58,T99	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T62,T83,T58	Yes	T62,T83,T58	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T60,*T75,*T77	Yes	T60,T75,T77	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T62,T99,T400	Yes	T62,T99,T400	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T62,T83,T58	Yes	T62,T83,T58	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T62,T83,T58	Yes	T62,T83,T58	INPUT
tl_kmac_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T62,T83,T99	Yes	T62,T83,T99	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T62,T83,T99	Yes	T62,T83,T99	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T62,T83,T58	Yes	T62,T99,T400	INPUT
tl_kmac_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T60,*T75,*T79	Yes	T60,T75,T77	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T62,*T83,*T58	Yes	T62,T99,T400	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T62,T83,T58	Yes	T62,T83,T58	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T58,T100,T59	Yes	T58,T100,T59	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T100,T59	Yes	T58,T100,T59	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T58,T100,T59	Yes	T58,T100,T59	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	INPUT
tl_aes_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T100,T101,T115	Yes	T100,T101,T115	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T100,T101,T115	Yes	T58,T100,T101	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T100,T101,T115	Yes	T58,T100,T101	INPUT
tl_aes_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T100,*T101,*T115	Yes	T100,T101,T115	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T100,T101,T115	Yes	T100,T101,T115	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T77	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T100,*T101,*T18	Yes	T52,T53,T100	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T100,T101,T115	Yes	T100,T101,T115	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T77	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T100,*T101,*T115	Yes	T100,T101,T115	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T75,T76,T117	Yes	T75,T76,T117	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T100,T101,T115	Yes	T100,T101,T115	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T79	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T77	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T79	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T100,*T101,*T115	Yes	T100,T101,T115	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	INPUT
tl_edn1_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T100,T101,T115	Yes	T100,T101,T115	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T100,T101,T115	Yes	T58,T100,T101	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T100,T101,T115	Yes	T58,T100,T101	INPUT
tl_edn1_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T100,*T101,*T115	Yes	T100,T101,T115	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T58,T100,T101	Yes	T58,T100,T101	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T31,*T75,*T77	Yes	T31,T75,T77	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T31,*T75,*T79	Yes	T31,T75,T77	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T5,*T16,*T17	Yes	T5,T16,T17	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T5,T16,T17	Yes	T5,T16,T17	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T78,*T186,*T187	Yes	T78,T186,T187	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	INPUT
tl_otbn_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T76,T77	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T52,T53,T101	Yes	T52,T53,T101	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T53,T101	Yes	T52,T53,T101	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T52,T58,T53	Yes	T52,T53,T101	INPUT
tl_otbn_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T78,*T186,*T187	Yes	T78,T186,T187	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T52,*T58,*T53	Yes	T52,T53,T101	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T83,T52,T58	Yes	T83,T52,T58	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T83,T52,T58	Yes	T83,T52,T58	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T58,T53,T100	Yes	T58,T53,T100	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T83,T52,T58	Yes	T83,T52,T58	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T83,T52,T58	Yes	T83,T52,T58	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T83,T52,T58	Yes	T83,T52,T58	INPUT
tl_keymgr_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T53,T100,T115	Yes	T53,T100,T115	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T53,T100	Yes	T52,T58,T53	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T52,T53,T100	Yes	T52,T58,T53	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T75,*T79,*T209	Yes	T75,T77,T79	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T52,*T53,*T100	Yes	T83,T52,T53	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T83,T52,T58	Yes	T83,T52,T58	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T243,*T75,*T76	Yes	T243,T75,T76	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T75,T76,T117	Yes	T75,T76,T117	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T17,T41,T52	Yes	T17,T41,T52	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T17,T41,T52	Yes	T17,T41,T52	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T243,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T62	Yes	T5,T6,T62	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T31,*T75,*T77	Yes	T31,T75,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T75,T77,T117	Yes	T75,T77,T117	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T31,T167,T302	Yes	T31,T167,T302	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T50,T51	Yes	T52,T58,T53	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T18,T50,T51	Yes	T52,T58,T53	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T31,*T75,*T79	Yes	T31,T75,T77	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T79,T116	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T111,*T31,*T271	Yes	T246,T111,T31	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T6,T41	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range