Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.37	90.68		89.43			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T41,T63,T234	Yes	T41,T63,T234	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T202	Yes	T52,T53,T202	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T52,T53,T202	Yes	T52,T53,T202	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	INPUT
tl_uart0_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T202,T18,T50	Yes	T202,T18,T50	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T202,T18,T50	Yes	T52,T58,T53	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T202,T18,T50	Yes	T52,T58,T53	INPUT
tl_uart0_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T77,T79	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T33,*T243,*T601	Yes	T33,T243,T601	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T202,*T18,*T50	Yes	T202,T18,T50	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T305,T33,T199	Yes	T305,T33,T199	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T305,T33,T199	Yes	T305,T33,T199	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T58,T59,T231	Yes	T58,T59,T231	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T58,T59,T231	Yes	T58,T59,T231	INPUT
tl_uart1_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T305,T33,T199	Yes	T305,T33,T199	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T231,T305,T33	Yes	T58,T59,T231	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T231,T305,T33	Yes	T58,T59,T231	INPUT
tl_uart1_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T33,*T75,*T79	Yes	T33,T75,T77	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T75,T79,T116	Yes	T75,T77,T79	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T305,*T33,*T199	Yes	T305,T33,T199	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T58,T59,T231	Yes	T58,T59,T231	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T140,T141,T316	Yes	T140,T141,T316	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T140,T141,T316	Yes	T140,T141,T316	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T58,T59,T140	Yes	T58,T59,T140	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T58,T59,T140	Yes	T58,T59,T140	INPUT
tl_uart2_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T140,T141,T316	Yes	T140,T141,T316	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T141,T231	Yes	T58,T59,T140	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T140,T141,T231	Yes	T58,T59,T140	INPUT
tl_uart2_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T33,*T75,*T76	Yes	T33,T75,T76	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T140,*T141,*T316	Yes	T140,T141,T316	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T58,T59,T140	Yes	T58,T59,T140	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T16,T25,T26	Yes	T16,T25,T26	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T16,T25,T26	Yes	T16,T25,T26	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T16,T58,T25	Yes	T16,T58,T25	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T16,T58,T25	Yes	T16,T58,T25	INPUT
tl_uart3_i.d_error	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T16,T25,T26	Yes	T16,T25,T26	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T25,T26	Yes	T16,T58,T25	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T16,T25,T26	Yes	T16,T58,T25	INPUT
tl_uart3_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T33,*T75,*T79	Yes	T33,T75,T77	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T16,*T25,*T26	Yes	T16,T25,T26	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T16,T58,T25	Yes	T16,T58,T25	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T197,T368,T306	Yes	T197,T368,T306	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T197,T368,T306	Yes	T197,T368,T306	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	INPUT
tl_i2c0_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T306,T307,T311	Yes	T306,T307,T311	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T197,T231,T368	Yes	T58,T197,T59	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T197,T231,T368	Yes	T58,T197,T59	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T77	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T79	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T197,*T368,*T306	Yes	T197,T368,T306	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T197,T368,T324	Yes	T197,T368,T324	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T197,T368,T324	Yes	T197,T368,T324	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	INPUT
tl_i2c1_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T324,T306,T307	Yes	T324,T306,T307	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T197,T231,T368	Yes	T58,T197,T59	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T197,T231,T368	Yes	T58,T197,T59	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T197,*T368,*T324	Yes	T197,T368,T324	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T197,T368,T306	Yes	T197,T368,T306	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T197,T368,T306	Yes	T197,T368,T306	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	INPUT
tl_i2c2_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T197,T231,T368	Yes	T58,T197,T59	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T197,T231,T368	Yes	T58,T197,T59	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T197,*T368,*T306	Yes	T197,T368,T306	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T58,T197,T59	Yes	T58,T197,T59	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T200,T337,T149	Yes	T200,T337,T149	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T200,T337,T149	Yes	T200,T337,T149	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T58,T59,T200	Yes	T58,T59,T200	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T58,T59,T200	Yes	T58,T59,T200	INPUT
tl_pattgen_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T200,T337,T149	Yes	T200,T337,T149	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T200,T337,T149	Yes	T58,T59,T200	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T200,T337,T149	Yes	T58,T59,T200	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T60,T75,T77	Yes	T60,T75,T77	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T200,*T337,*T149	Yes	T200,T337,T149	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T58,T59,T200	Yes	T58,T59,T200	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T142,T201,T657	Yes	T142,T201,T657	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T142,T201,T657	Yes	T142,T201,T657	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T58,T59,T142	Yes	T58,T59,T142	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T58,T59,T142	Yes	T58,T59,T142	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T142,T201,T657	Yes	T142,T201,T657	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T142,T201,T657	Yes	T58,T59,T142	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T142,T201,T657	Yes	T58,T59,T142	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	T75,*T79,*T116	Yes	T75,T77,T79	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T142,*T201,*T657	Yes	T142,T201,T657	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T58,T59,T142	Yes	T58,T59,T142	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	INPUT
tl_gpio_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T34,T35,T306	Yes	T34,T35,T306	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T35,T306	Yes	T58,T59,T142	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T34,T35,T306	Yes	T58,T59,T142	INPUT
tl_gpio_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T75,*T77,*T79	Yes	T75,T77,T79	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T6,*T41,*T58	Yes	T5,T6,T62	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T5,T197,T22	Yes	T5,T197,T22	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T5,T197,T22	Yes	T5,T197,T22	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T5,T58,T197	Yes	T5,T58,T197	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T5,T58,T197	Yes	T5,T58,T197	INPUT
tl_spi_device_i.d_error	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T5,T197,T22	Yes	T5,T197,T22	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T197,T22	Yes	T5,T197,T22	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T5,T58,T197	Yes	T5,T197,T22	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T31,*T75,*T79	Yes	T31,T75,T77	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T5,*T58,*T197	Yes	T5,T197,T22	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T5,T58,T197	Yes	T5,T58,T197	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T241,T142,T238	Yes	T241,T142,T238	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T241,T142,T238	Yes	T241,T142,T238	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T58,T241,T59	Yes	T58,T241,T59	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T58,T241,T59	Yes	T58,T241,T59	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T241,T238,T239	Yes	T241,T238,T239	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T241,T142,T238	Yes	T58,T241,T59	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T241,T142,T238	Yes	T58,T241,T59	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T31,*T75,*T79	Yes	T31,T75,T77	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T241,*T142,*T238	Yes	T241,T142,T238	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T58,T241,T59	Yes	T58,T241,T59	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T52,T27,T53	Yes	T52,T27,T53	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T52,T27,T53	Yes	T52,T27,T53	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T52,T58,T27	Yes	T52,T58,T27	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T52,T58,T27	Yes	T52,T58,T27	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T27,T1,T97	Yes	T27,T1,T97	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T27,T53	Yes	T52,T58,T27	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T52,T27,T53	Yes	T52,T58,T27	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T79,T116	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T75,*T79,*T116	Yes	T75,T77,T79	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T52,*T27,*T53	Yes	T52,T27,T53	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T52,T58,T27	Yes	T52,T58,T27	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T79,T116,T492	Yes	T77,T79,T116	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T41,T52	Yes	T5,T6,T62	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T6,T41,T52	Yes	T5,T6,T62	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T75,*T79,*T116	Yes	T75,T77,T79	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T62	Yes	T5,T6,T62	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T16,T56,T58	Yes	T16,T56,T58	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T16,T56,T58	Yes	T16,T56,T58	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T79,T116	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T16,T56,T102	Yes	T16,T56,T102	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T16	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T6,T16	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T76,T79	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T75,*T79,*T116	Yes	T75,T79,T116	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T16,*T56,*T102	Yes	T16,T56,T102	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T79	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T60,*T75,*T76	Yes	T60,T75,T76	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T79	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T146,*T60,*T147	Yes	T146,T60,T147	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T83,*T58,*T100	Yes	T83,T100,T148	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T60,T75,T77	Yes	T60,T75,T77	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T60,T75,T77	Yes	T60,T75,T77	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T60,T75,T77	Yes	T60,T75,T77	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T5,T6,T62	Yes	T5,T6,T62	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T5,T6,T62	Yes	T6,T41,T27	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T60,T75,T76	Yes	T60,T75,T77	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T75,T76	Yes	T60,T75,T117	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T5,T6,T62	Yes	T6,T41,T27	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T76,T79	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T60,T75,T79	Yes	T60,T75,T77	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T75,T79,T116	Yes	T75,T76,T79	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T62	Yes	T6,T41,T27	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T60,T75,T77	Yes	T60,T75,T77	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T6,T83,T52	Yes	T6,T83,T52	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T6,T83,T52	Yes	T6,T83,T52	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T6,T83,T52	Yes	T6,T83,T52	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T6,T83,T52	Yes	T6,T83,T52	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T6,T52,T53	Yes	T6,T83,T52	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T55,T173	Yes	T6,T58,T55	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T6,T52,T53	Yes	T6,T83,T52	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T70,*T242,*T354	Yes	T70,T242,T354	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T6,*T18,*T55	Yes	T6,T83,T52	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T6,T83,T52	Yes	T6,T83,T52	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T134,T1,T118	Yes	T134,T1,T118	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T134,T1,T118	Yes	T58,T134,T1	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T31,*T75,*T79	Yes	T31,T75,T79	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T41	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T41,T52,T58	Yes	T41,T52,T58	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T41,T52,T58	Yes	T41,T52,T58	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T41,T52,T58	Yes	T41,T52,T58	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T41,T52,T58	Yes	T41,T52,T58	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T41,T52,T58	Yes	T41,T52,T58	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T52,T58	Yes	T41,T52,T58	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T41,T52,T53	Yes	T41,T52,T58	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T41,*T58,*T97	Yes	T41,T52,T58	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T41,T52,T58	Yes	T41,T52,T58	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T18	Yes	T52,T53,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T52,T53,T18	Yes	T52,T53,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T163,T164,T111	Yes	T163,T164,T111	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T163,T50	Yes	T52,T58,T53	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T18,T163,T50	Yes	T52,T58,T53	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T31,*T75,*T76	Yes	T31,T75,T76	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T163,*T164,*T111	Yes	T163,T164,T111	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T52,T58,T53	Yes	T52,T58,T53	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T41,T83	Yes	T4,T41,T83	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T6,T41	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T41,T83	Yes	T4,T41,T83	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T4,T41,T52	Yes	T4,T41,T52	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T76,T79	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T78,*T186,*T187	Yes	T78,T186,T187	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T75,T79,T116	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T62	Yes	T5,T6,T62	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T41,T52,T53	Yes	T41,T52,T53	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T41,T52,T53	Yes	T41,T52,T53	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T41,T52,T58	Yes	T41,T52,T58	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T41,T52,T58	Yes	T41,T52,T58	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T41,T1,T97	Yes	T41,T1,T97	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T52,T53	Yes	T41,T52,T58	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T41,T52,T53	Yes	T41,T52,T58	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T69,T668,T243	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T41,*T52,*T53	Yes	T41,T52,T53	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T41,T52,T58	Yes	T41,T52,T58	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T64,T29	Yes	T1,T64,T29	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T64,T29	Yes	T1,T64,T29	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T58,T1,T64	Yes	T58,T1,T64	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T58,T1,T64	Yes	T58,T1,T64	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T64,T29	Yes	T1,T64,T29	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T64,T29	Yes	T58,T1,T64	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T64,T29,T30	Yes	T58,T1,T64	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T75,T79,T116	Yes	T75,T77,T79	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T31,*T33,*T75	Yes	T31,T33,T75	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T77,T79	Yes	T75,T77,T79	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T64,*T29	Yes	T1,T64,T29	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T58,T1,T64	Yes	T58,T1,T64	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T103,T3	Yes	T1,T103,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T103,T3	Yes	T1,T103,T3	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T58,T1,T59	Yes	T58,T1,T59	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T58,T1,T59	Yes	T58,T1,T59	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T103,T3	Yes	T1,T103,T3	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T103,T3	Yes	T58,T1,T59	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T103,T3	Yes	T58,T1,T59	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T77	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T103,*T3	Yes	T1,T103,T3	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T58,T1,T59	Yes	T58,T1,T59	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T31	Yes	T69,T70,T31	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T31,T33,T78	Yes	T31,T33,T78	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T75,T117,T79	Yes	T75,T117,T79	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T4,T6,T41	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T75,T77,T79	Yes	T75,T79,T116	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T75,*T79,*T116	Yes	T75,T77,T79	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T75,T79,T116	Yes	T75,T79,T116	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T75,*T77,*T117	Yes	T75,T117,T79	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range