Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3600207	1			T74	259		T75	13936		T76	86
values[2]	716490	1			T74	528		T75	1920		T76	34
values[3]	102206	1			T74	476		T75	47		T76	1
values[4]	55967	1			T74	326		T75	26		T78	249
values[5]	38099	1			T74	274		T75	19		T78	124
values[6]	28694	1			T74	207		T75	11		T78	82
values[7]	23176	1			T74	100		T75	34		T78	80
values[8]	19679	1			T74	86		T75	28		T78	76
values[9]	17409	1			T74	63		T75	26		T78	65
values[10]	15923	1			T74	55		T75	10		T78	43
values[11]	14679	1			T74	40		T75	22		T78	27
values[12]	13574	1			T74	36		T75	9		T78	26
values[13]	13172	1			T74	13		T75	15		T78	26
values[14]	12441	1			T74	10		T75	24		T78	38
values[15]	11844	1			T74	7		T75	30		T78	26
values[16]	11721	1			T74	5		T75	14		T78	22
values[17]	11499	1			T74	8		T75	11		T78	27
values[18]	10983	1			T74	5		T75	15		T78	15
values[19]	10897	1			T74	3		T75	31		T78	6
values[20]	10227	1			T74	6		T75	16		T78	8
values[21]	9747	1			T74	7		T75	28		T78	14
values[22]	9588	1			T74	4		T75	32		T78	22
values[23]	9258	1			T74	10		T75	24		T78	9
values[24]	8911	1			T74	14		T75	10		T78	13
values[25]	8758	1			T74	28		T75	12		T78	19
values[26]	8314	1			T74	38		T75	18		T78	22
values[27]	7999	1			T74	25		T75	13		T78	13
values[28]	7365	1			T74	16		T75	13		T78	10
values[29]	6715	1			T74	7		T75	13		T78	6
values[30]	6415	1			T74	6		T75	17		T78	9
values[31]	6218	1			T74	5		T75	21		T78	8
values[32]	5637	1			T74	7		T75	1		T78	6
values[33]	5339	1			T74	3		T75	1		T78	15
values[34]	4831	1			T74	3		T75	8		T78	17
values[35]	4466	1			T74	5		T75	16		T78	22
values[36]	4247	1			T74	2		T75	4		T78	13
values[37]	4000	1			T74	2		T75	3		T78	10
values[38]	3751	1			T74	1		T75	3		T78	10
values[39]	3488	1			T74	2		T75	2		T78	6
values[40]	3516	1			T74	3		T78	7		T249	2
values[41]	3462	1			T74	2		T78	9		T249	2
values[42]	3450	1			T74	1		T78	18		T249	1
values[43]	3320	1			T74	1		T78	14		T249	1
values[44]	3296	1			T74	1		T78	7		T249	1
values[45]	3207	1			T74	2		T78	13		T249	7
values[46]	3093	1			T74	1		T78	10		T249	5
values[47]	3185	1			T74	2		T78	9		T249	3
values[48]	3071	1			T74	2		T78	19		T249	5
values[49]	2932	1			T74	3		T78	19		T249	1
values[50]	2919	1			T74	1		T78	11		T249	2
values[51]	2771	1			T74	2		T78	7		T249	8
values[52]	2733	1			T74	1		T78	7		T558	13
values[53]	2712	1			T74	1		T78	13		T558	16
values[54]	2676	1			T74	2		T78	8		T558	11
values[55]	2695	1			T74	2		T78	5		T558	12
values[56]	2563	1			T74	2		T78	9		T558	7
values[57]	2449	1			T74	1		T78	7		T558	11
values[58]	2507	1			T74	2		T78	9		T558	12
values[59]	2430	1			T74	4		T78	13		T558	10
values[60]	2397	1			T74	4		T78	4		T558	10
values[61]	2723	1			T74	4		T78	9		T558	5
values[62]	4117	1			T74	2		T78	18		T558	13
values[63]	11190	1			T74	5		T78	105		T558	41
values[64]	233157	1			T74	78		T78	266		T558	144

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4655377	1			T74	1787		T75	14865		T76	85
values[2]	795910	1			T74	494		T75	1884		T76	35
values[3]	84155	1			T74	94		T75	36		T76	10
values[4]	14608	1			T74	29		T75	2		T76	3
values[5]	5356	1			T74	25		T76	1		T78	7
values[6]	3247	1			T74	18		T78	7		T79	1
values[7]	2354	1			T74	18		T78	7		T240	3
values[8]	2025	1			T74	18		T78	12		T558	7
values[9]	1717	1			T74	13		T78	13		T558	20
values[10]	1457	1			T74	25		T78	7		T558	12
values[11]	1312	1			T74	26		T78	5		T558	5
values[12]	1228	1			T74	22		T78	2		T558	7
values[13]	1154	1			T74	14		T78	6		T558	7
values[14]	1059	1			T74	11		T78	4		T558	4
values[15]	991	1			T74	13		T78	4		T558	9
values[16]	909	1			T74	14		T78	3		T558	4
values[17]	854	1			T74	18		T78	5		T558	2
values[18]	881	1			T74	12		T78	7		T558	7
values[19]	912	1			T74	12		T78	7		T558	7
values[20]	897	1			T74	10		T78	9		T558	3
values[21]	824	1			T74	13		T78	3		T558	2
values[22]	816	1			T74	16		T78	10		T558	2
values[23]	726	1			T74	17		T78	3		T558	3
values[24]	731	1			T74	17		T78	2		T558	6
values[25]	718	1			T74	7		T78	1		T558	10
values[26]	710	1			T74	5		T78	2		T558	20
values[27]	726	1			T78	2		T558	25		T451	19
values[28]	715	1			T78	1		T558	8		T451	26
values[29]	643	1			T78	1		T558	8		T451	8
values[30]	628	1			T78	1		T558	8		T451	7
values[31]	564	1			T78	2		T558	1		T451	4
values[32]	575	1			T78	1		T558	4		T451	3
values[33]	526	1			T78	3		T558	3		T451	2
values[34]	514	1			T78	15		T558	1		T451	4
values[35]	529	1			T78	10		T558	5		T475	8
values[36]	492	1			T78	6		T558	4		T475	2
values[37]	473	1			T78	19		T475	3		T828	3
values[38]	528	1			T78	13		T475	1		T828	3
values[39]	510	1			T78	5		T828	3		T477	1
values[40]	468	1			T78	9		T828	3		T477	1
values[41]	474	1			T78	11		T828	3		T477	1
values[42]	423	1			T78	2		T828	3		T477	1
values[43]	434	1			T78	6		T828	3		T477	1
values[44]	437	1			T78	5		T828	3		T477	1
values[45]	415	1			T78	3		T828	3		T477	2
values[46]	427	1			T78	2		T828	3		T477	2
values[47]	407	1			T78	1		T828	3		T477	2
values[48]	410	1			T78	4		T828	4		T477	1
values[49]	404	1			T78	1		T828	3		T477	1
values[50]	397	1			T78	2		T828	3		T477	2
values[51]	402	1			T828	3		T477	1		T835	5
values[52]	394	1			T828	3		T477	1		T835	6
values[53]	381	1			T828	3		T477	3		T835	1
values[54]	387	1			T828	3		T477	3		T835	2
values[55]	377	1			T828	3		T477	1		T835	6
values[56]	385	1			T828	3		T477	3		T835	2
values[57]	348	1			T828	3		T477	3		T835	1
values[58]	335	1			T828	3		T477	1		T835	1
values[59]	352	1			T828	3		T477	4		T841	1
values[60]	360	1			T828	3		T477	3		T841	1
values[61]	420	1			T828	3		T477	2		T841	1
values[62]	689	1			T828	3		T477	2		T841	1
values[63]	2577	1			T828	3		T477	8		T841	1
values[64]	28115	1			T828	570		T477	91		T841	146

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	542962	1			T74	12		T75	2648		T76	1
values[2]	2570409	1			T74	143		T75	10471		T76	39
values[3]	1138818	1			T74	448		T75	1841		T76	32
values[4]	144288	1			T74	477		T75	25		T76	2
values[5]	75707	1			T74	395		T75	28		T76	1
values[6]	49545	1			T74	282		T75	26		T78	124
values[7]	35789	1			T74	206		T75	20		T78	51
values[8]	28344	1			T74	158		T75	24		T78	23
values[9]	24114	1			T74	79		T75	21		T78	11
values[10]	20724	1			T74	47		T75	37		T78	14
values[11]	18842	1			T74	29		T75	38		T78	17
values[12]	17665	1			T74	24		T75	25		T78	22
values[13]	16662	1			T74	20		T75	23		T78	11
values[14]	15693	1			T74	32		T75	28		T78	17
values[15]	14467	1			T74	27		T75	32		T78	26
values[16]	13394	1			T74	31		T75	18		T78	19
values[17]	12893	1			T74	31		T75	11		T78	9
values[18]	12439	1			T74	21		T75	8		T78	13
values[19]	12156	1			T74	17		T75	19		T78	18
values[20]	11568	1			T74	18		T75	17		T78	22
values[21]	11401	1			T74	30		T75	6		T78	20
values[22]	11148	1			T74	21		T75	8		T78	25
values[23]	10926	1			T74	17		T75	7		T78	27
values[24]	10279	1			T74	18		T75	13		T78	30
values[25]	9796	1			T74	24		T75	15		T78	17
values[26]	9554	1			T74	20		T75	18		T78	23
values[27]	8926	1			T74	12		T75	20		T78	18
values[28]	8138	1			T74	10		T75	19		T78	18
values[29]	7637	1			T74	12		T75	8		T78	13
values[30]	7180	1			T74	8		T75	13		T78	15
values[31]	6722	1			T74	3		T75	16		T78	17
values[32]	6081	1			T74	5		T75	9		T78	25
values[33]	5746	1			T74	3		T75	6		T78	20
values[34]	5239	1			T74	1		T75	4		T78	17
values[35]	4935	1			T74	1		T75	6		T78	14
values[36]	4487	1			T74	2		T75	2		T78	9
values[37]	4307	1			T74	1		T75	4		T78	15
values[38]	4303	1			T74	9		T75	9		T78	14
values[39]	4038	1			T74	6		T75	3		T78	9
values[40]	3740	1			T74	5		T75	3		T78	9
values[41]	3705	1			T74	5		T75	4		T78	13
values[42]	3612	1			T74	2		T75	2		T78	10
values[43]	3506	1			T74	4		T75	5		T78	11
values[44]	3566	1			T74	2		T75	2		T78	13
values[45]	3573	1			T74	2		T75	6		T78	16
values[46]	3494	1			T74	2		T75	10		T78	12
values[47]	3391	1			T74	1		T75	2		T78	13
values[48]	3396	1			T74	2		T75	2		T78	25
values[49]	3281	1			T74	1		T75	3		T78	14
values[50]	3188	1			T74	4		T75	2		T78	5
values[51]	3105	1			T74	1		T75	1		T78	8
values[52]	3039	1			T74	1		T75	3		T78	14
values[53]	2990	1			T74	8		T75	2		T78	19
values[54]	3021	1			T74	3		T75	7		T78	16
values[55]	2841	1			T74	6		T75	4		T78	12
values[56]	2831	1			T74	6		T75	1		T78	13
values[57]	2734	1			T74	3		T78	14		T239	3
values[58]	2703	1			T74	1		T78	17		T239	3
values[59]	2731	1			T74	1		T78	20		T239	2
values[60]	2762	1			T74	2		T78	7		T239	2
values[61]	2890	1			T74	1		T78	9		T239	3
values[62]	3665	1			T74	2		T78	13		T239	2
values[63]	9577	1			T74	15		T78	66		T239	1
values[64]	227350	1			T74	75		T78	164		T239	8