Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2018077	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31537312

1

T4

4225

T5

9628

T6

13191

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	22701772	1			T4	1353		T5	3568		T6	5363
values[0x0]	9153036	1			T4	2872		T5	6060		T6	7828
values[0x1]	1700581	1			T4	202		T5	600		T6	903

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	505871	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

33049518

1

T4

4427

T5

10228

T6

14094

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15780880	1			T4	2214		T5	5115		T6	7048
valid_sources[0x01]	15778846	1			T4	2213		T5	5113		T6	7046
valid_sources[0x02]	32675	1			T139	3272		T891	2		T140	408
valid_sources[0x03]	31814	1			T139	3200		T891	3		T140	428
valid_sources[0x04]	32472	1			T139	3233		T891	3		T560	10
valid_sources[0x05]	31880	1			T139	3241		T891	3		T140	425
valid_sources[0x06]	31626	1			T139	3335		T891	8		T560	2
valid_sources[0x07]	31797	1			T139	3150		T891	4		T140	366
valid_sources[0x08]	35508	1			T54	39		T139	3283		T891	2
valid_sources[0x09]	31356	1			T458	3		T139	3501		T891	4
valid_sources[0x0a]	32228	1			T10	1		T139	3379		T891	5
valid_sources[0x0b]	32000	1			T139	3299		T891	10		T140	405
valid_sources[0x0c]	32841	1			T139	3561		T891	4		T560	3
valid_sources[0x0d]	30934	1			T139	3214		T891	8		T560	6
valid_sources[0x0e]	31981	1			T139	3484		T891	3		T140	390
valid_sources[0x0f]	32509	1			T139	3153		T891	2		T140	395
valid_sources[0x10]	33914	1			T458	3		T139	3566		T891	2
valid_sources[0x11]	31558	1			T458	5		T139	3092		T891	2
valid_sources[0x12]	32688	1			T187	39		T139	3596		T891	2
valid_sources[0x13]	32551	1			T458	2		T139	3264		T891	4
valid_sources[0x14]	32706	1			T139	3400		T891	5		T140	401
valid_sources[0x15]	32420	1			T458	5		T139	3265		T891	4
valid_sources[0x16]	32134	1			T56	39		T139	3275		T891	4
valid_sources[0x17]	31951	1			T139	3560		T891	5		T560	2
valid_sources[0x18]	33306	1			T458	4		T139	3377		T891	4
valid_sources[0x19]	32906	1			T186	39		T458	1		T139	3267
valid_sources[0x1a]	32157	1			T139	2973		T891	7		T560	10
valid_sources[0x1b]	31904	1			T139	3201		T891	3		T560	42
valid_sources[0x1c]	32026	1			T139	2990		T891	3		T140	395
valid_sources[0x1d]	31587	1			T139	3285		T891	5		T140	444
valid_sources[0x1e]	31596	1			T139	3164		T891	3		T560	4
valid_sources[0x1f]	31869	1			T10	3		T139	3492		T891	3
valid_sources[0x20]	31605	1			T10	8		T139	2733		T891	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22172759

1

T4

1353

T5

3568

T6

5363

values[0x0]

all_enables

biggest_size

9110025

1

T4

2872

T5

6060

T6

7828

values[0x1]

all_enables

biggest_size

254528

1

T54

19

T56

17

T10

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2828945	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

448829

1

T74

377

T75

2201

T76

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1109261	1			T74	946		T75	5459		T76	34
values[0x0]	1058546	1			T74	923		T75	5474		T76	43
values[0x1]	1109967	1			T74	952		T75	5550		T76	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2189976	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1087798

1

T74

950

T75

5430

T76

44

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51628	1			T74	48		T75	273		T76	2
valid_sources[0x01]	50867	1			T74	41		T75	312		T76	2
valid_sources[0x02]	52311	1			T74	48		T75	278		T76	1
valid_sources[0x03]	51744	1			T74	73		T75	197		T76	1
valid_sources[0x04]	51350	1			T74	28		T75	239		T78	44
valid_sources[0x05]	52186	1			T74	70		T75	240		T76	1
valid_sources[0x06]	51616	1			T74	47		T75	315		T78	28
valid_sources[0x07]	51889	1			T74	45		T75	244		T76	2
valid_sources[0x08]	52167	1			T74	74		T75	290		T76	1
valid_sources[0x09]	50830	1			T74	24		T75	315		T78	49
valid_sources[0x0a]	51389	1			T74	30		T75	294		T78	36
valid_sources[0x0b]	51200	1			T74	18		T75	222		T76	4
valid_sources[0x0c]	50764	1			T74	36		T75	278		T76	1
valid_sources[0x0d]	51821	1			T74	53		T75	199		T76	5
valid_sources[0x0e]	50750	1			T74	36		T75	252		T78	35
valid_sources[0x0f]	51270	1			T74	28		T75	286		T76	2
valid_sources[0x10]	51237	1			T74	52		T75	243		T78	63
valid_sources[0x11]	51029	1			T74	43		T75	255		T76	2
valid_sources[0x12]	50898	1			T74	52		T75	262		T76	3
valid_sources[0x13]	50166	1			T74	35		T75	247		T76	1
valid_sources[0x14]	51872	1			T74	51		T75	216		T76	1
valid_sources[0x15]	51585	1			T74	52		T75	285		T76	3
valid_sources[0x16]	50115	1			T74	66		T75	247		T78	31
valid_sources[0x17]	50823	1			T74	30		T75	227		T78	27
valid_sources[0x18]	51524	1			T74	31		T75	252		T76	5
valid_sources[0x19]	50649	1			T74	60		T75	283		T78	33
valid_sources[0x1a]	51042	1			T74	33		T75	294		T76	1
valid_sources[0x1b]	50541	1			T74	51		T75	291		T76	2
valid_sources[0x1c]	51295	1			T74	41		T75	248		T78	43
valid_sources[0x1d]	52272	1			T74	53		T75	321		T78	43
valid_sources[0x1e]	51349	1			T74	48		T75	229		T78	24
valid_sources[0x1f]	51222	1			T74	27		T75	216		T76	1
valid_sources[0x20]	52065	1			T74	58		T75	281		T78	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47165

1

T74

34

T75

201

T76

2

values[0x0]

all_enables

biggest_size

354456

1

T74

309

T75

1759

T76

12

values[0x1]

all_enables

biggest_size

47208

1

T74

34

T75

241

T78

37

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3030302	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

492649

1

T74

406

T75

2415

T76

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1204873	1			T74	969		T75	5713		T76	46
values[0x0]	1111896	1			T74	885		T75	5466		T76	53
values[0x1]	1206182	1			T74	894		T75	5608		T76	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2324019	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1198932

1

T74

952

T75

5787

T76

51

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55969	1			T74	35		T75	251		T76	1
valid_sources[0x01]	55960	1			T74	40		T75	323		T76	3
valid_sources[0x02]	55848	1			T74	44		T75	250		T78	37
valid_sources[0x03]	55746	1			T74	42		T75	216		T78	44
valid_sources[0x04]	55148	1			T74	35		T75	291		T76	3
valid_sources[0x05]	55208	1			T74	51		T75	255		T76	5
valid_sources[0x06]	55524	1			T74	35		T75	340		T76	1
valid_sources[0x07]	55823	1			T74	45		T75	201		T76	3
valid_sources[0x08]	55350	1			T74	45		T75	182		T76	2
valid_sources[0x09]	55080	1			T74	40		T75	331		T78	42
valid_sources[0x0a]	55165	1			T74	57		T75	276		T78	37
valid_sources[0x0b]	55233	1			T74	42		T75	179		T76	1
valid_sources[0x0c]	55317	1			T74	42		T75	258		T76	5
valid_sources[0x0d]	54106	1			T74	38		T75	187		T76	3
valid_sources[0x0e]	55320	1			T74	38		T75	294		T78	44
valid_sources[0x0f]	55508	1			T74	33		T75	260		T78	72
valid_sources[0x10]	56908	1			T74	44		T75	216		T76	3
valid_sources[0x11]	55320	1			T74	40		T75	249		T78	36
valid_sources[0x12]	54802	1			T74	41		T75	295		T76	4
valid_sources[0x13]	54520	1			T74	40		T75	280		T76	1
valid_sources[0x14]	54284	1			T74	48		T75	297		T78	25
valid_sources[0x15]	55871	1			T74	47		T75	242		T76	1
valid_sources[0x16]	53671	1			T74	34		T75	263		T76	2
valid_sources[0x17]	54263	1			T74	48		T75	197		T76	2
valid_sources[0x18]	54524	1			T74	50		T75	236		T76	4
valid_sources[0x19]	54267	1			T74	34		T75	253		T76	2
valid_sources[0x1a]	55534	1			T74	37		T75	211		T76	1
valid_sources[0x1b]	55247	1			T74	45		T75	318		T76	4
valid_sources[0x1c]	54538	1			T74	37		T75	221		T76	3
valid_sources[0x1d]	56259	1			T74	44		T75	276		T78	35
valid_sources[0x1e]	54902	1			T74	47		T75	221		T76	3
valid_sources[0x1f]	54606	1			T74	48		T75	330		T76	3
valid_sources[0x20]	55557	1			T74	43		T75	303		T76	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51540

1

T74

43

T75

243

T76

3

values[0x0]

all_enables

biggest_size

389486

1

T74

330

T75

1934

T76

23

values[0x1]

all_enables

biggest_size

51623

1

T74

33

T75

238

T78

35

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2852224	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

452725

1

T74

398

T75

2173

T76

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1117544	1			T74	988		T75	5227		T76	26
values[0x0]	1069286	1			T74	923		T75	5209		T76	21
values[0x1]	1118119	1			T74	944		T75	5169		T76	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2207798	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1097151

1

T74

954

T75

5162

T76

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52654	1			T74	48		T75	216		T76	4
valid_sources[0x01]	52001	1			T74	44		T75	300		T76	2
valid_sources[0x02]	52336	1			T74	44		T75	278		T78	47
valid_sources[0x03]	52274	1			T74	41		T75	181		T78	38
valid_sources[0x04]	51688	1			T74	45		T75	201		T78	44
valid_sources[0x05]	51589	1			T74	51		T75	243		T78	28
valid_sources[0x06]	51091	1			T74	40		T75	263		T78	52
valid_sources[0x07]	51652	1			T74	47		T75	251		T78	39
valid_sources[0x08]	51842	1			T74	46		T75	215		T78	53
valid_sources[0x09]	52002	1			T74	43		T75	281		T76	1
valid_sources[0x0a]	51102	1			T74	50		T75	282		T78	40
valid_sources[0x0b]	52556	1			T74	44		T75	219		T76	2
valid_sources[0x0c]	52587	1			T74	44		T75	318		T76	1
valid_sources[0x0d]	51543	1			T74	50		T75	217		T78	42
valid_sources[0x0e]	51600	1			T74	37		T75	268		T76	3
valid_sources[0x0f]	50984	1			T74	30		T75	220		T78	42
valid_sources[0x10]	51575	1			T74	57		T75	214		T78	37
valid_sources[0x11]	51365	1			T74	49		T75	233		T78	48
valid_sources[0x12]	51340	1			T74	47		T75	233		T78	41
valid_sources[0x13]	51565	1			T74	40		T75	230		T78	39
valid_sources[0x14]	51521	1			T74	51		T75	230		T76	1
valid_sources[0x15]	52272	1			T74	48		T75	269		T76	3
valid_sources[0x16]	51451	1			T74	43		T75	250		T78	30
valid_sources[0x17]	52080	1			T74	54		T75	202		T78	37
valid_sources[0x18]	51070	1			T74	31		T75	220		T78	35
valid_sources[0x19]	51543	1			T74	40		T75	302		T78	27
valid_sources[0x1a]	51943	1			T74	40		T75	239		T78	37
valid_sources[0x1b]	51520	1			T74	41		T75	297		T78	39
valid_sources[0x1c]	51772	1			T74	51		T75	253		T78	45
valid_sources[0x1d]	52448	1			T74	64		T75	265		T78	32
valid_sources[0x1e]	51252	1			T74	36		T75	193		T76	3
valid_sources[0x1f]	51492	1			T74	44		T75	197		T76	2
valid_sources[0x20]	51787	1			T74	42		T75	277		T76	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47665

1

T74

46

T75

227

T78

32

values[0x0]

all_enables

biggest_size

357464

1

T74

306

T75

1728

T76

6

values[0x1]

all_enables

biggest_size

47596

1

T74

46

T75

218

T78

31