Module Definition
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Module : hmac
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_hmac 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_hmac

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : hmac
TotalCoveredPercent
Totals 33 33 100.00
Total Bits 316 316 100.00
Total Bits 0->1 158 158 100.00
Total Bits 1->0 158 158 100.00

Ports 33 33 100.00
Port Bits 316 316 100.00
Port Bits 0->1 158 158 100.00
Port Bits 1->0 158 158 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T6,T18 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T5,T6,T18 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T51,T714,T57 Yes T51,T714,T57 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T51,T714,T57 Yes T51,T714,T57 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T51,T714,T165 Yes T51,T714,T165 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T51,T714,T57 Yes T51,T714,T57 INPUT
tl_i.a_mask[3:0] Yes Yes T51,T714,T165 Yes T51,T714,T165 INPUT
tl_i.a_address[12:0] Yes Yes *T75,*T76,*T79 Yes T75,T76,T79 INPUT
tl_i.a_address[15:13] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T51,*T714,*T165 Yes T51,T714,T165 INPUT
tl_i.a_address[19:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T51,*T714,*T165 Yes T51,T714,T165 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T51,*T714,*T165 Yes T51,T714,T165 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T51,*T714,*T165 Yes T51,T714,T165 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T10,*T75,*T76 Yes T10,T75,T76 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T76,T79 Yes T75,T76,T79 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T714,T325,T715 Yes T714,T325,T715 INPUT
tl_i.a_valid Yes Yes T51,T714,T165 Yes T51,T714,T165 INPUT
tl_o.a_ready Yes Yes T51,T714,T165 Yes T51,T714,T165 OUTPUT
tl_o.d_error Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T51,T714,T165 Yes T51,T714,T165 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T51,T714,T165 Yes T51,T714,T165 OUTPUT
tl_o.d_data[31:0] Yes Yes T51,T714,T57 Yes T51,T714,T52 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
tl_o.d_source[5:0] Yes Yes *T10,*T75,*T76 Yes T10,T75,T76 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T51,*T714,*T57 Yes T51,T714,T52 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T51,T714,T165 Yes T51,T714,T165 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T63,T57,T81 Yes T63,T57,T81 INPUT
alert_rx_i[0].ping_n Yes Yes T81,T410,T82 Yes T81,T410,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T81,T410,T82 Yes T81,T410,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T63,T57,T81 Yes T63,T57,T81 OUTPUT
intr_hmac_done_o Yes Yes T325,T321,T349 Yes T325,T321,T349 OUTPUT
intr_fifo_empty_o Yes Yes T321,T324,T329 Yes T321,T324,T329 OUTPUT
intr_hmac_err_o Yes Yes T321,T324,T329 Yes T321,T324,T329 OUTPUT
idle_o[3:0] Yes Yes T4,T5,T6 Yes T5,T6,T18 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%