Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : adc_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_adc_ctrl_aon 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_adc_ctrl_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : adc_ctrl
TotalCoveredPercent
Totals 37 37 100.00
Total Bits 324 324 100.00
Total Bits 0->1 162 162 100.00
Total Bits 1->0 162 162 100.00

Ports 37 37 100.00
Port Bits 324 324 100.00
Port Bits 0->1 162 162 100.00
Port Bits 1->0 162 162 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T6,T18 Yes T4,T5,T6 INPUT
rst_aon_ni Yes Yes T5,T6,T18 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T54,T7,T95 Yes T54,T7,T95 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T54,T7,T95 Yes T54,T7,T95 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[6:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
tl_i.a_address[17:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[21:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T54,*T67,*T77 Yes T54,T67,T77 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T54,T56,T10 Yes T54,T56,T10 INPUT
tl_i.a_valid Yes Yes T54,T57,T7 Yes T54,T57,T7 INPUT
tl_o.a_ready Yes Yes T54,T57,T7 Yes T54,T57,T7 OUTPUT
tl_o.d_error Yes Yes T75,T76,T78 Yes T75,T78,T79 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T54,T95,T1 Yes T54,T7,T95 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T54,T7,T95 Yes T54,T57,T7 OUTPUT
tl_o.d_data[31:0] Yes Yes T54,T7,T95 Yes T54,T57,T7 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T78 Yes T75,T76,T78 OUTPUT
tl_o.d_source[5:0] Yes Yes *T54,*T75,*T78 Yes T54,T75,T76 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T78 Yes T75,T76,T78 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T54,*T95,*T1 Yes T54,T7,T95 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T54,T57,T7 Yes T54,T57,T7 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T57,T81,T82 Yes T57,T81,T82 INPUT
alert_rx_i[0].ping_n Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T57,T81,T82 Yes T57,T81,T82 OUTPUT
adc_o.pd Yes Yes T95,T1,T2 Yes T95,T1,T2 OUTPUT
adc_o.channel_sel[1:0] Yes Yes T95,T1,T2 Yes T95,T1,T2 OUTPUT
adc_i.data_valid Yes Yes T95,T1,T2 Yes T95,T1,T2 INPUT
adc_i.data[9:0] Yes Yes T95,T1,T2 Yes T95,T1,T2 INPUT
intr_match_pending_o Yes Yes T95,T321,T361 Yes T95,T321,T361 OUTPUT
wkup_req_o Yes Yes T1,T2,T16 Yes T95,T1,T2 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%