Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473016638	53739642	0	0
DepthKnown_A	473016638	472911982	0	0
RvalidKnown_A	473016638	472911982	0	0
WreadyKnown_A	473016638	472911982	0	0
gen_passthru_fifo.paramCheckPass	983	983	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	53739642	0	0
T4	75388	8674	0	0
T5	199084	17616	0	0
T6	229194	29949	0	0
T18	224183	29568	0	0
T51	130538	143422	0	0
T85	380511	53535	0	0
T86	88453	10498	0	0
T87	378852	53333	0	0
T88	154449	19412	0	0
T89	348656	33158	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473016638	40877026	0	0
DepthKnown_A	473016638	472911982	0	0
RvalidKnown_A	473016638	472911982	0	0
WreadyKnown_A	473016638	472911982	0	0
gen_passthru_fifo.paramCheckPass	983	983	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	40877026	0	0
T4	75388	6314	0	0
T5	199084	13831	0	0
T6	229194	20400	0	0
T18	224183	19899	0	0
T51	130538	124442	0	0
T85	380511	46634	0	0
T86	88453	7986	0	0
T87	378852	50177	0	0
T88	154449	16874	0	0
T89	348656	28927	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473016638	35594523	0	0
DepthKnown_A	473016638	472911982	0	0
RvalidKnown_A	473016638	472911982	0	0
WreadyKnown_A	473016638	472911982	0	0
gen_passthru_fifo.paramCheckPass	983	983	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	35594523	0	0
T4	75388	4562	0	0
T5	199084	10525	0	0
T6	229194	14476	0	0
T18	224183	14052	0	0
T51	130538	170509	0	0
T85	380511	43247	0	0
T86	88453	5711	0	0
T87	378852	47653	0	0
T88	154449	6337	0	0
T89	348656	31434	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473016638	31595437	0	0
DepthKnown_A	473016638	472911982	0	0
RvalidKnown_A	473016638	472911982	0	0
WreadyKnown_A	473016638	472911982	0	0
gen_passthru_fifo.paramCheckPass	983	983	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	31595437	0	0
T4	75388	4427	0	0
T5	199084	10228	0	0
T6	229194	14094	0	0
T18	224183	13665	0	0
T51	130538	115914	0	0
T85	380511	42833	0	0
T86	88453	5550	0	0
T87	378852	47496	0	0
T88	154449	6159	0	0
T89	348656	31100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	472911982	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	548749618	89489	0	0
DepthKnown_A	548749618	548633176	0	0
RvalidKnown_A	548749618	548633176	0	0
WreadyKnown_A	548749618	548633176	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	89489	0	0
T4	75388	13	0	0
T5	199084	28	0	0
T6	229194	151	0	0
T18	224183	151	0	0
T51	130538	34	0	0
T85	380511	39	0	0
T86	88453	13	0	0
T87	378852	13	0	0
T88	154449	48	0	0
T89	348656	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	548749618	92220	0	0
DepthKnown_A	548749618	548633176	0	0
RvalidKnown_A	548749618	548633176	0	0
WreadyKnown_A	548749618	548633176	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	92220	0	0
T4	75388	13	0	0
T5	199084	28	0	0
T6	229194	151	0	0
T18	224183	151	0	0
T51	130538	34	0	0
T85	380511	39	0	0
T86	88453	13	0	0
T87	378852	13	0	0
T88	154449	48	0	0
T89	348656	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	548749618	51726	0	0
DepthKnown_A	548749618	548633176	0	0
RvalidKnown_A	548749618	548633176	0	0
WreadyKnown_A	548749618	548633176	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	51726	0	0
T4	75388	12	0	0
T5	199084	26	0	0
T6	229194	95	0	0
T18	224183	95	0	0
T51	130538	5	0	0
T85	380511	37	0	0
T86	88453	12	0	0
T87	378852	12	0	0
T88	154449	47	0	0
T89	348656	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	548749618	51726	0	0
DepthKnown_A	548749618	548633176	0	0
RvalidKnown_A	548749618	548633176	0	0
WreadyKnown_A	548749618	548633176	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	51726	0	0
T4	75388	12	0	0
T5	199084	26	0	0
T6	229194	95	0	0
T18	224183	95	0	0
T51	130538	5	0	0
T85	380511	37	0	0
T86	88453	12	0	0
T87	378852	12	0	0
T88	154449	47	0	0
T89	348656	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	548749618	37763	0	0
DepthKnown_A	548749618	548633176	0	0
RvalidKnown_A	548749618	548633176	0	0
WreadyKnown_A	548749618	548633176	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	37763	0	0
T4	75388	1	0	0
T5	199084	2	0	0
T6	229194	56	0	0
T18	224183	56	0	0
T51	130538	29	0	0
T85	380511	2	0	0
T86	88453	1	0	0
T87	378852	1	0	0
T88	154449	1	0	0
T89	348656	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	548749618	40494	0	0
DepthKnown_A	548749618	548633176	0	0
RvalidKnown_A	548749618	548633176	0	0
WreadyKnown_A	548749618	548633176	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	40494	0	0
T4	75388	1	0	0
T5	199084	2	0	0
T6	229194	56	0	0
T18	224183	56	0	0
T51	130538	29	0	0
T85	380511	2	0	0
T86	88453	1	0	0
T87	378852	1	0	0
T88	154449	1	0	0
T89	348656	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	548749618	548633176	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0