Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	INPUT
tl_i.a_valid	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	INPUT
tl_o.a_ready	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T113,T54,T200	Yes	T113,T54,T200	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T74,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T51,*T113	Yes	T4,T51,T113	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T308,T57	Yes	T54,T308,T57	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T308,T57	Yes	T54,T308,T57	OUTPUT
cio_rx_i	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T51,T113,T54	Yes	T51,T113,T54	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T113,T54,T200	Yes	T113,T54,T200	OUTPUT
intr_tx_empty_o	Yes	Yes	T113,T54,T200	Yes	T113,T54,T200	OUTPUT
intr_rx_watermark_o	Yes	Yes	T113,T200,T115	Yes	T113,T200,T115	OUTPUT
intr_tx_done_o	Yes	Yes	T4,T113,T200	Yes	T4,T113,T200	OUTPUT
intr_rx_overflow_o	Yes	Yes	T4,T113,T200	Yes	T4,T113,T200	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_break_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_timeout_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	INPUT
tl_i.a_valid	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	INPUT
tl_o.a_ready	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T113,T54,T205	Yes	T113,T54,T205	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T74,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T51,*T113	Yes	T4,T51,T113	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
cio_rx_i	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T51,T113,T54	Yes	T51,T113,T54	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T113,T205,T307	Yes	T113,T205,T307	OUTPUT
intr_tx_empty_o	Yes	Yes	T113,T205,T275	Yes	T113,T205,T275	OUTPUT
intr_rx_watermark_o	Yes	Yes	T113,T205,T275	Yes	T113,T205,T275	OUTPUT
intr_tx_done_o	Yes	Yes	T4,T113,T286	Yes	T4,T113,T286	OUTPUT
intr_rx_overflow_o	Yes	Yes	T4,T113,T286	Yes	T4,T113,T286	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_break_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_timeout_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T54,T200,T115	Yes	T54,T200,T115	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T54,T200,T115	Yes	T54,T200,T115	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	INPUT
tl_i.a_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
tl_o.a_ready	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T54,T200,T115	Yes	T54,T200,T115	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T54,T149,T200	Yes	T54,T57,T149	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T54,T149,T200	Yes	T54,T57,T149	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T74,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T54,*T200,*T115	Yes	T54,T200,T115	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T308,T57,T149	Yes	T308,T57,T149	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T308,T57,T149	Yes	T308,T57,T149	OUTPUT
cio_rx_i	Yes	Yes	T200,T115,T201	Yes	T200,T115,T201	INPUT
cio_tx_o	Yes	Yes	T54,T200,T115	Yes	T54,T200,T115	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T54,T200,T115	Yes	T54,T200,T115	OUTPUT
intr_tx_empty_o	Yes	Yes	T54,T200,T115	Yes	T54,T200,T115	OUTPUT
intr_rx_watermark_o	Yes	Yes	T200,T115,T201	Yes	T200,T115,T201	OUTPUT
intr_tx_done_o	Yes	Yes	T200,T115,T201	Yes	T200,T115,T201	OUTPUT
intr_rx_overflow_o	Yes	Yes	T200,T115,T201	Yes	T200,T115,T201	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_break_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_timeout_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T54,T142,T143	Yes	T54,T142,T143	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T54,T142,T143	Yes	T54,T142,T143	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	INPUT
tl_i.a_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
tl_o.a_ready	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T54,T142,T143	Yes	T54,T142,T143	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T54,T149,T142	Yes	T54,T57,T149	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T54,T149,T142	Yes	T54,T57,T149	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T74,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T54,*T142,*T143	Yes	T54,T142,T143	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T149,T81	Yes	T57,T149,T81	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T149,T81	Yes	T57,T149,T81	OUTPUT
cio_rx_i	Yes	Yes	T142,T143,T188	Yes	T142,T143,T188	INPUT
cio_tx_o	Yes	Yes	T54,T142,T143	Yes	T54,T142,T143	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T142,T143,T188	Yes	T142,T143,T188	OUTPUT
intr_tx_empty_o	Yes	Yes	T54,T142,T143	Yes	T54,T142,T143	OUTPUT
intr_rx_watermark_o	Yes	Yes	T142,T143,T188	Yes	T142,T143,T188	OUTPUT
intr_tx_done_o	Yes	Yes	T142,T143,T188	Yes	T142,T143,T188	OUTPUT
intr_rx_overflow_o	Yes	Yes	T142,T143,T188	Yes	T142,T143,T188	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_break_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_timeout_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T54,T28,T29	Yes	T54,T28,T29	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T54,T28,T29	Yes	T54,T28,T29	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	INPUT
tl_i.a_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
tl_o.a_ready	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
tl_o.d_error	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T54,T28,T29	Yes	T54,T28,T29	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T54,T149,T28	Yes	T54,T57,T149	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T54,T149,T28	Yes	T54,T57,T149	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T79,T249	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T75,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T54,*T28,*T29	Yes	T54,T28,T29	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
cio_rx_i	Yes	Yes	T28,T29,T323	Yes	T28,T29,T323	INPUT
cio_tx_o	Yes	Yes	T28,T29,T323	Yes	T28,T29,T323	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T54,T28,T29	Yes	T54,T28,T29	OUTPUT
intr_tx_empty_o	Yes	Yes	T54,T28,T29	Yes	T54,T28,T29	OUTPUT
intr_rx_watermark_o	Yes	Yes	T28,T29,T323	Yes	T28,T29,T323	OUTPUT
intr_tx_done_o	Yes	Yes	T28,T29,T323	Yes	T28,T29,T323	OUTPUT
intr_rx_overflow_o	Yes	Yes	T28,T29,T323	Yes	T28,T29,T323	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_break_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_timeout_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T322,T326,T327	Yes	T322,T326,T327	OUTPUT

*Tests covering at least one bit in the range