Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_por_aon_n_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T26
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T26

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	16126	15661	0	0
selKnown1	125701	124392	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	16126	15661	0	0
T20	6	5	0	0
T24	251	250	0	0
T27	32	31	0	0
T39	14	12	0	0
T40	11	9	0	0
T41	26	24	0	0
T54	2	1	0	0
T55	16	15	0	0
T62	4	3	0	0
T64	29	28	0	0
T67	1	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	14	0	0
T114	1	0	0	0
T158	1	0	0	0
T163	0	2	0	0
T174	2	4	0	0
T175	2	1	0	0
T176	8	7	0	0
T177	3	2	0	0
T178	5	4	0	0
T179	13	12	0	0
T180	4	3	0	0
T181	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	125701	124392	0	0
T5	3	2	0	0
T6	2	1	0	0
T18	2	1	0	0
T19	0	1	0	0
T20	0	5	0	0
T39	10	8	0	0
T40	24	22	0	0
T41	13	11	0	0
T42	545	544	0	0
T51	1	0	0	0
T54	0	1	0	0
T63	0	1	0	0
T85	2	1	0	0
T86	1	0	0	0
T87	1	0	0	0
T88	1	0	0	0
T89	1	0	0	0
T113	1	0	0	0
T165	0	1	0	0
T174	23	21	0	0
T175	35	33	0	0
T176	17	29	0	0
T177	8	20	0	0
T178	9	19	0	0
T179	11	25	0	0
T180	11	10	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T20,T54
0	1	Covered	T27,T20,T54
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T20,T54
1	1	Covered	T27,T20,T54

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	987	864	0	0
selKnown1	1713	740	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	987	864	0	0
T20	6	5	0	0
T27	32	31	0	0
T54	2	1	0	0
T55	16	15	0	0
T62	4	3	0	0
T64	29	28	0	0
T67	1	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	14	0	0
T114	1	0	0	0
T158	1	0	0	0
T163	0	2	0	0
T181	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1713	740	0	0
T5	3	2	0	0
T6	2	1	0	0
T18	2	1	0	0
T19	0	1	0	0
T20	0	5	0	0
T51	1	0	0	0
T54	0	1	0	0
T63	0	1	0	0
T85	2	1	0	0
T86	1	0	0	0
T87	1	0	0	0
T88	1	0	0	0
T89	1	0	0	0
T113	1	0	0	0
T165	0	1	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2769	2752	0	0
selKnown1	674	655	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2769	2752	0	0
T22	1	0	0	0
T24	251	250	0	0
T25	262	261	0	0
T26	239	238	0	0
T39	12	11	0	0
T40	9	8	0	0
T41	18	17	0	0
T174	0	3	0	0
T183	750	749	0	0
T184	19	18	0	0
T185	1139	1138	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	674	655	0	0
T21	1	0	0	0
T23	1	0	0	0
T39	5	4	0	0
T40	14	13	0	0
T41	6	5	0	0
T42	545	544	0	0
T174	13	12	0	0
T175	18	17	0	0
T176	0	13	0	0
T177	0	13	0	0
T178	0	11	0	0
T179	0	15	0	0
T184	1	0	0	0
T185	1	0	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T22,T23,T39
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T42,T21,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T22,T23,T39

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	51	39	0	0
selKnown1	108	95	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	51	39	0	0
T39	2	1	0	0
T40	2	1	0	0
T41	8	7	0	0
T174	2	1	0	0
T175	2	1	0	0
T176	8	7	0	0
T177	3	2	0	0
T178	5	4	0	0
T179	13	12	0	0
T180	4	3	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	108	95	0	0
T39	5	4	0	0
T40	10	9	0	0
T41	7	6	0	0
T174	10	9	0	0
T175	17	16	0	0
T176	17	16	0	0
T177	8	7	0	0
T178	9	8	0	0
T179	11	10	0	0
T180	11	10	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2792	2776	0	0
selKnown1	166	153	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2792	2776	0	0
T24	269	268	0	0
T25	245	244	0	0
T26	241	240	0	0
T39	11	10	0	0
T40	8	7	0	0
T41	16	15	0	0
T174	8	7	0	0
T183	797	796	0	0
T184	19	18	0	0
T185	1108	1107	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	166	153	0	0
T39	10	9	0	0
T40	16	15	0	0
T41	8	7	0	0
T42	2	1	0	0
T43	1	0	0	0
T44	1	0	0	0
T174	20	19	0	0
T175	16	15	0	0
T176	19	18	0	0
T177	10	9	0	0
T178	0	9	0	0
T179	0	35	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T39,T40,T41
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T42,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T39,T40,T41

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	51	41	0	0
selKnown1	145	132	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	51	41	0	0
T39	3	2	0	0
T40	3	2	0	0
T41	12	11	0	0
T174	2	1	0	0
T175	7	6	0	0
T176	8	7	0	0
T177	3	2	0	0
T179	11	10	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	145	132	0	0
T39	8	7	0	0
T40	10	9	0	0
T41	9	8	0	0
T174	15	14	0	0
T175	10	9	0	0
T176	21	20	0	0
T177	6	5	0	0
T178	16	15	0	0
T179	27	26	0	0
T180	20	19	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T22,T39,T40
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	3086	3070	0	0
selKnown1	164	153	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	3086	3070	0	0
T24	353	352	0	0
T25	409	408	0	0
T26	361	360	0	0
T39	10	9	0	0
T40	9	8	0	0
T41	12	11	0	0
T174	10	9	0	0
T175	0	6	0	0
T183	732	731	0	0
T184	1	0	0	0
T185	1122	1121	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	164	153	0	0
T39	6	5	0	0
T40	22	21	0	0
T41	8	7	0	0
T174	20	19	0	0
T175	21	20	0	0
T176	15	14	0	0
T177	16	15	0	0
T178	14	13	0	0
T179	29	28	0	0
T180	12	11	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T22,T39,T40
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	59	43	0	0
selKnown1	136	125	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	59	43	0	0
T22	1	0	0	0
T24	3	2	0	0
T25	3	2	0	0
T26	3	2	0	0
T40	3	2	0	0
T41	6	5	0	0
T174	2	1	0	0
T176	7	6	0	0
T177	0	2	0	0
T183	3	2	0	0
T185	3	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	136	125	0	0
T39	6	5	0	0
T40	17	16	0	0
T41	6	5	0	0
T174	17	16	0	0
T175	19	18	0	0
T176	17	16	0	0
T177	7	6	0	0
T178	13	12	0	0
T179	22	21	0	0
T180	11	10	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T42,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	3112	3095	0	0
selKnown1	292	279	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	3112	3095	0	0
T23	1	0	0	0
T24	371	370	0	0
T25	393	392	0	0
T26	364	363	0	0
T39	10	9	0	0
T40	8	7	0	0
T41	17	16	0	0
T174	0	7	0	0
T175	0	6	0	0
T183	781	780	0	0
T184	1	0	0	0
T185	1092	1091	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	292	279	0	0
T22	1	0	0	0
T23	1	0	0	0
T39	3	2	0	0
T40	22	21	0	0
T41	5	4	0	0
T42	124	123	0	0
T174	21	20	0	0
T175	25	24	0	0
T176	22	21	0	0
T177	11	10	0	0
T178	0	14	0	0
T179	0	22	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T42,T22,T23
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	57	41	0	0
selKnown1	128	115	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	57	41	0	0
T22	1	0	0	0
T23	1	0	0	0
T24	3	2	0	0
T25	3	2	0	0
T26	3	2	0	0
T39	5	4	0	0
T40	4	3	0	0
T41	3	2	0	0
T174	0	1	0	0
T175	0	2	0	0
T183	3	2	0	0
T185	3	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	128	115	0	0
T39	6	5	0	0
T40	14	13	0	0
T41	6	5	0	0
T174	11	10	0	0
T175	14	13	0	0
T176	14	13	0	0
T177	8	7	0	0
T178	17	16	0	0
T179	19	18	0	0
T180	16	15	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T54,T42,T56
0	1	Covered	T42,T43,T21
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T54,T42,T56
1	1	Covered	T42,T43,T21

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	755	733	0	0
selKnown1	2605	2578	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	755	733	0	0
T10	1	0	0	0
T21	1	0	0	0
T22	1	0	0	0
T23	1	0	0	0
T39	0	19	0	0
T40	0	23	0	0
T41	0	21	0	0
T42	546	545	0	0
T43	1	0	0	0
T44	1	0	0	0
T56	1	0	0	0
T174	0	27	0	0
T175	0	24	0	0
T176	0	17	0	0
T177	0	10	0	0
T178	0	17	0	0
T179	0	12	0	0
T186	1	0	0	0
T187	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2605	2578	0	0
T21	1	0	0	0
T22	1	0	0	0
T24	214	213	0	0
T25	226	225	0	0
T26	202	201	0	0
T39	0	6	0	0
T40	0	6	0	0
T41	0	13	0	0
T42	1	0	0	0
T43	1	0	0	0
T44	1	0	0	0
T56	1	0	0	0
T174	0	6	0	0
T175	0	4	0	0
T183	732	731	0	0
T185	0	1121	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T54,T42,T56
0	1	Covered	T42,T43,T21
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T54,T42,T56
1	1	Covered	T42,T43,T21

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	754	732	0	0
selKnown1	2610	2583	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	754	732	0	0
T10	1	0	0	0
T21	1	0	0	0
T22	1	0	0	0
T23	1	0	0	0
T39	0	18	0	0
T40	0	24	0	0
T41	0	19	0	0
T42	546	545	0	0
T43	1	0	0	0
T44	1	0	0	0
T56	1	0	0	0
T174	0	28	0	0
T175	0	24	0	0
T176	0	17	0	0
T177	0	10	0	0
T178	0	16	0	0
T179	0	13	0	0
T186	1	0	0	0
T187	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2610	2583	0	0
T21	1	0	0	0
T22	1	0	0	0
T24	214	213	0	0
T25	226	225	0	0
T26	202	201	0	0
T39	0	6	0	0
T40	0	7	0	0
T41	0	14	0	0
T42	1	0	0	0
T43	1	0	0	0
T44	1	0	0	0
T56	1	0	0	0
T174	0	6	0	0
T175	0	5	0	0
T183	732	731	0	0
T185	0	1121	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T54,T42,T21
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T54,T42,T21
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	229	202	0	0
selKnown1	2621	2593	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	229	202	0	0
T10	1	0	0	0
T14	2	1	0	0
T21	1	0	0	0
T39	0	14	0	0
T40	0	11	0	0
T41	0	24	0	0
T42	2	1	0	0
T43	1	0	0	0
T44	1	0	0	0
T56	1	0	0	0
T174	0	27	0	0
T175	0	11	0	0
T176	0	30	0	0
T177	0	8	0	0
T178	0	23	0	0
T184	1	0	0	0
T185	1	0	0	0
T186	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2621	2593	0	0
T21	1	0	0	0
T22	1	0	0	0
T24	232	231	0	0
T25	210	209	0	0
T26	205	204	0	0
T39	0	5	0	0
T40	0	6	0	0
T41	0	16	0	0
T42	1	0	0	0
T43	1	0	0	0
T44	1	0	0	0
T56	1	0	0	0
T174	0	4	0	0
T175	0	8	0	0
T183	781	780	0	0
T185	0	1091	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T54,T42,T21
0	1	Covered	T24,T25,T26
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T54,T42,T21
1	1	Covered	T24,T25,T26

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	232	205	0	0
selKnown1	2616	2588	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	232	205	0	0
T10	1	0	0	0
T14	2	1	0	0
T21	1	0	0	0
T39	0	13	0	0
T40	0	10	0	0
T41	0	24	0	0
T42	2	1	0	0
T43	1	0	0	0
T44	1	0	0	0
T56	1	0	0	0
T174	0	28	0	0
T175	0	12	0	0
T176	0	29	0	0
T177	0	8	0	0
T178	0	24	0	0
T184	1	0	0	0
T185	1	0	0	0
T186	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2616	2588	0	0
T21	1	0	0	0
T22	1	0	0	0
T24	232	231	0	0
T25	210	209	0	0
T26	205	204	0	0
T39	0	4	0	0
T40	0	5	0	0
T41	0	15	0	0
T42	1	0	0	0
T43	1	0	0	0
T44	1	0	0	0
T56	1	0	0	0
T174	0	3	0	0
T175	0	9	0	0
T183	781	780	0	0
T185	0	1091	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T54,T21,T56
0	1	Covered	T21,T22,T23
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T54,T21,T56
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	160	141	0	0
selKnown1	27919	27889	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	160	141	0	0
T39	8	7	0	0
T40	9	8	0	0
T41	19	18	0	0
T174	10	9	0	0
T175	19	18	0	0
T176	23	22	0	0
T177	6	5	0	0
T178	15	14	0	0
T179	26	25	0	0
T180	16	15	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27919	27889	0	0
T24	387	386	0	0
T25	443	442	0	0
T26	395	394	0	0
T48	20	19	0	0
T138	2002	2001	0	0
T146	1646	1645	0	0
T147	1649	1648	0	0
T183	749	748	0	0
T188	4698	4697	0	0
T189	4706	4705	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T54,T21,T56
0	1	Covered	T21,T22,T23
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T54,T21,T56
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	165	146	0	0
selKnown1	27919	27889	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	165	146	0	0
T39	9	8	0	0
T40	9	8	0	0
T41	17	16	0	0
T174	10	9	0	0
T175	20	19	0	0
T176	24	23	0	0
T177	6	5	0	0
T178	16	15	0	0
T179	28	27	0	0
T180	17	16	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27919	27889	0	0
T24	387	386	0	0
T25	443	442	0	0
T26	395	394	0	0
T48	20	19	0	0
T138	2002	2001	0	0
T146	1646	1645	0	0
T147	1649	1648	0	0
T183	749	748	0	0
T188	4698	4697	0	0
T189	4706	4705	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T54,T190,T31
0	1	Covered	T24,T190,T31
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T54,T190,T31
1	1	Covered	T24,T190,T31

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	433	390	0	0
selKnown1	27943	27913	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	433	390	0	0
T25	1	0	0	0
T26	1	0	0	0
T31	1	0	0	0
T32	1	0	0	0
T33	8	7	0	0
T42	0	120	0	0
T183	1	0	0	0
T190	25	24	0	0
T191	2	1	0	0
T192	2	1	0	0
T193	2	1	0	0
T194	0	7	0	0
T195	0	27	0	0
T196	0	1	0	0
T197	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27943	27913	0	0
T24	405	404	0	0
T25	426	425	0	0
T26	397	396	0	0
T48	20	19	0	0
T138	2002	2001	0	0
T146	1646	1645	0	0
T147	1649	1648	0	0
T183	796	795	0	0
T188	4698	4697	0	0
T189	4706	4705	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T54,T190,T31
0	1	Covered	T24,T190,T31
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T54,T190,T31
1	1	Covered	T24,T190,T31

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	434	391	0	0
selKnown1	27942	27912	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	434	391	0	0
T25	1	0	0	0
T26	1	0	0	0
T31	1	0	0	0
T32	1	0	0	0
T33	8	7	0	0
T42	0	120	0	0
T183	1	0	0	0
T190	25	24	0	0
T191	2	1	0	0
T192	2	1	0	0
T193	2	1	0	0
T194	0	7	0	0
T195	0	27	0	0
T196	0	1	0	0
T197	0	7	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27942	27912	0	0
T24	405	404	0	0
T25	426	425	0	0
T26	397	396	0	0
T48	20	19	0	0
T138	2002	2001	0	0
T146	1646	1645	0	0
T147	1649	1648	0	0
T183	796	795	0	0
T188	4698	4697	0	0
T189	4706	4705	0	0